XC2S30-5CS144I datasheet, PDF - EEWORLD Datasheet

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XC2S30-5CS144I: DescriptionField Programmable Gate Array, 216 CLBs, 30000 Gates, 263MHz, 972-Cell, CMOS, PBGA144, CHIP SCALE, BGA-144; File Size76KB，6 Pages; ManufacturerXILINX; Websitehttps://www.xilinx.com/

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XC2S30-5CS144I Overview

Field Programmable Gate Array, 216 CLBs, 30000 Gates, 263MHz, 972-Cell, CMOS, PBGA144, CHIP SCALE, BGA-144

XC2S30-5CS144I Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Objectid	1544609784
Parts packaging code	BGA
Contacts	144
Reach Compliance Code	not_compliant
Country Of Origin	Taiwan
ECCN code	EAR99
Factory Lead Time	52 weeks
Samacsys Manufacturer	XILINX
Samacsys Modified On	2022-06-22 13:28:30
YTEOL	3
maximum clock frequency	263 MHz
Combined latency of CLB-Max	0.7 ns
JESD-30 code	S-PBGA-B144
JESD-609 code	e0
length	12 mm
Humidity sensitivity level	3
Configurable number of logic blocks	216
Equivalent number of gates	30000
Number of entries	96
Number of logical units	972
Output times	92
Number of terminals	144
Maximum operating temperature	100 °C
Minimum operating temperature	-40 °C
organize	216 CLBS, 30000 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Encapsulate equivalent code	BGA144,13X13,32
Package shape	SQUARE
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	240
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage	2.625 V
Minimum supply voltage	2.375 V
Nominal supply voltage	2.5 V
surface mount	YES
Terminal surface	TIN LEAD
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	12 mm

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— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —

Spartan-IIE 1.8V FPGA

Automotive XA Product Family:

Introduction and Ordering

DS106-1 (v2.0) August 9, 2013

Product Specification

•

Guaranteed to meet full electrical specifications over

= –40°C to +125°C

Second generation ASIC replacement technology

- Densities as high as 6,912 logic cells with up to

300,000 system gates

- Very low cost

System-level features

- SelectRAM+™ hierarchical memory:

16 bits/LUT distributed RAM

Configurable 4K-bit true dual-port block RAM

Fast interfaces to external RAM

- Dedicated carry logic for high-speed arithmetic

- Efficient multiplier support

- Cascade chain for wide-input functions

- Abundant registers/latches with enable, set, reset

- Four dedicated DLLs for advanced clock control

Eliminate clock distribution delay

Multiply, divide, or phase shift

- Four primary low-skew global clock distribution nets

- IEEE 1149.1 compatible boundary scan logic

Versatile I/O and packaging

- Low-cost packages available in all densities

- 19 high-performance interface standards

LVTTL, LVCMOS, HSTL, SSTL, AGP, CTT, GTL

LVDS and LVPECL differential I/O

- Up to 120 differential I/O pairs that can be input,

output, or bidirectional

Fully supported by powerful Xilinx ISE development

system

- Fully automatic mapping, placement, and routing

- Integrated with design entry and verification tools

- Extensive IP library including DSP functions

Introduction

The Xilinx Automotive (XA) Spartan™-IIE 1.8V Field-Pro-

grammable Gate Array family is specifically designed to

meet the needs of high-volume, cost-sensitive automotive

electronic applications. The family gives users high perfor-

mance, abundant logic resources, and a rich feature set, all

at an exceptionally low price. The five-member family offers

densities ranging from 50,000 to 300,000 system gates, as

shown in

Table 1.

System performance is supported beyond

200 MHz.

Spartan-IIE devices deliver more gates, I/Os, and features

per dollar than other FPGAs by combining advanced pro-

cess technology with a streamlined architecture based on

the proven Virtex™-E platform. Features include block RAM

(to 64K bits), distributed RAM (to 98,304 bits), 19 selectable

I/O standards, and four DLLs (Delay-Locked Loops). Fast,

predictable interconnect means that successive design iter-

ations continue to meet timing requirements.

XA devices are available in both the extended-temperature

Q-grade (-40

C to +125

C) and industrial I-grade (-40

C to

+100

C) and are qualified to the industry-recognized

AEC-Q100 standard.

The XA Spartan-IIE family is a superior alternative to

mask-programmed ASICs. The FPGA avoids the initial cost,

lengthy development cycles, and inherent risk of conven-

tional ASICs. Also, FPGA programmability permits design

upgrades in the field with no hardware replacement neces-

sary (impossible with ASICs).

•

Features

•

AEC-Q100 device qualification and full PPAP support

available in both extended temperature Q-grade and

I-grade

Table 1:

XA Spartan-IIE FPGA Family Members

Logic

Cells

1,728

2,700

3,888

5,292

6,912

Typical

System Gate Range

(Logic and RAM)

23,000 - 50,000

37,000 - 100,000

52,000 - 150,000

71,000 - 200,000

93,000 - 300,000

CLB

Array

(R x C)

16 x 24

20 x 30

24 x 36

28 x 42

32 x 48

Total

CLBs

384

600

864

1,176

1,536

Maximum

Available

User I/O

(1)

102

182

Maximum

Differential

I/O Pairs

114

120

Distributed

RAM Bits

24,576

38,400

55,296

75,264

98,304

Block

RAM Bits

32K

40K

48K

56K

64K

Device

XA2S50E

XA2S100E

XA2S150E

XA2S200E

XA2S300E

Notes:

1. User I/O counts include the four global clock/user input pins. See details in

Table 3, page 5

http://www.xilinx.com/legal.htm.

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS106-1 (v2.0) August 9, 2013

Product Specification

www.xilinx.com

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