PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8343I-01
L
OW
S
KEW
, 1-
TO
-16
LVCMOS / LVTTL F
ANOUT
B
UFFER
F
EATURES
• 16 LVCMOS/LVTTL outputs
• 1 LVCMOS/LVTTL clock input
• CLK can accept the following input levels: LVCMOS, LVTTL
• Maximum output frequency: 200MHz
• Dual output enable inputs facilitates 1-to-16 or 1-to-8 input
to output modes
• All inputs are 5V tolerant
• Output skew: 250ps (typical)
• Part-to-part skew: 700ps (typical)
• Full 3.3V and 2.5V or mixed 3.3V core/2.5V operating supply
• -40°C to 85°C ambient operating temperature
G
ENERAL
D
ESCRIPTION
The ICS8343I-01 is a low skew, 1-to-16
LVCMOS/LVTTL Fanout Buffer and a member of
HiPerClockS™
the HiPerClockS™ family of High Performance
Clock Solutions from ICS. The ICS8343I-01
single ended clock input accepts LVCMOS or
LVTTL input levels. The ICS8343I-01 operates at 3.3V,
2.5V and mixed 3.3V input and 2.5V supply modes over the
commercial temperature range. Guaranteed output and part-
to-part skew characteristics make the ICS8343I-01 ideal for
those clock distribution applications demanding well defined
performance and repeatability.
ICS
B
LOCK
D
IAGRAM
VDD1
V
DD1
P
IN
A
SSIGNMENT
OE1
OE2
Q15
Q14
Q13
DD
VDD
V
VDD2
V
DD2
Q2
CLK
CLK
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
Q7
Q7
Q15
Q15
Q14
Q14
Q13
Q13
Q12
Q12
Q11
Q11
Q10
Q10
Q9
Q9
Q8
Q8
32 31 30 29 28 27 26 25
V
DD
1
V
DD
1
V
DD
1
Q3
Q4
GND
GND
GND
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
Q5
Q6
Q7
CLK
V
DD
Q8
Q9
Q10
ICS8343I-01
OE1
OE1
GND
GND
OE2
OE2
32-Lead LQFP
7mm x 7mm x 1.4mm body package
Y Package
(Top View)
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8343AYI-01
Q1
Q0
24
23
22
21
20
19
18
17
V
DD
2
V
DD
2
V
DD
2
Q12
Q11
GND
GND
GND
www.icst.com/products/hiperclocks.html
1
REV. A JUNE 22, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8343I-01
L
OW
S
KEW
, 1-
TO
-16
LVCMOS / LVTTL F
ANOUT
B
UFFER
Type
Power
Output
Power
Output
Input
Power
Output
Output
Power
Output
Description
Q0 thru Q7 output supply pins.
LVCMOS/LVTTL clock outputs. 7
Ω
typical output impedance.
Power supply ground.
LVCMOS/LVTTL clock outputs. 7
Ω
typical output impedance.
Pulldown LVCMOS/LVTTL clock input / 5V tolerant.
Core supply pin.
LVCMOS/LVTTL clock outputs. 7
Ω
typical output impedance.
LVCMOS/LVTTL clock outputs. 7
Ω
typical output impedance.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2, 3
4, 5
6, 7, 8,
17, 18, 19
9, 10, 11
12
13
14, 15, 16
20, 21
22, 23, 24
25, 26, 27
Name
V
DD1
Q3, Q4
GND
Q5, Q6, Q7
CLK
V
DD
Q8, Q9, Q10
Q11, Q12
V
DD2
Q13, Q14, Q15
Q8 thru Q15 output supply pins.
LVCMOS/LVTTL clock outputs. 7
Ω
typical output impedance.
Output enable. When low forces outputs Q8 thru Q15 to HiZ state.
28
OE2
Input
Pullup
5V tolerant. LVCMOS/LVTTL interface levels.
Output enable. When low forces outputs Q0 thru Q7 to HiZ state.
29
OE1
Input
Pullup
5V tolerant. LVCMOS/LVTTL interface levels.
30, 31, 32
Q0, Q1, Q2
Output
LVCMOS/LVTTL clock outputs. 7
Ω
typical output impedance.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
V
DD
, V
DD1
, V
DD2
= 3.3V
5
V
DD
, V
DD1
, V
DD2
= 3.465V
V
DD1
, V
DD2
= 2.63V
Test Conditions
Minimum
Typical
4
11
9
51
51
7
12
Maximum
Units
pF
pF
pF
KΩ
KΩ
Ω
T
ABLE
3. F
UNCTION
T
ABLE
Inputs
OE1
0
1
0
1
OE2
0
0
1
1
HiZ
Active
HiZ
Active
Outputs
Q0:Q7
Q8:Q15
HiZ
HiZ
Active
Active
NOTE: OE1 and OE2 are 5V tolerant.
8343AYI-01
www.icst.com/products/hiperclocks.html
2
REV. A JUNE 22, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8343I-01
L
OW
S
KEW
, 1-
TO
-16
LVCMOS / LVTTL F
ANOUT
B
UFFER
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDx
+ 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DD1
= V
DD2
= 3.3V±5%, T
A
= -40°
TO
85°C
Symbol
V
DD
V
DDx
I
DD
Parameter
Core Supply Voltage
Output Supply Voltage; NOTE 1
Power Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
35
14
Units
V
V
mA
mA
I
DDx
Output Supply Current; NOTE 2
NOTE 1: V
DDx
denotes V
DD1
and V
DD2
.
NOTE 2: I
DDx
denotes the sum of I
DD1
and I
DD2
.
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DD1
= V
DD2
= 3.3V±5%, T
A
= -40°
TO
85°C
Symbol Parameter
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
I
OZL
I
OZH
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
OE1, OE2
CLK
OE1, OE2
CLK
OE1, OE2
CLK
OE1, OE2
CLK
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-150
-5
2.6
0.5
5
5
Test Conditions
Minimum
2
2
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0. 8
1.3
5
150
Units
V
V
V
V
µA
µA
µA
µA
V
V
µA
µA
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output Tristate Current Low
Output Tristate Current High
NOTE 1: Outputs terminated with 50
Ω
to V
DDx
/2. See Parameter Measurement Information, 3.3V Output Load Test Circuit.
8343AYI-01
www.icst.com/products/hiperclocks.html
3
REV. A JUNE 22, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8343I-01
L
OW
S
KEW
, 1-
TO
-16
LVCMOS / LVTTL F
ANOUT
B
UFFER
Test Conditions
Minimum
3.135
2.375
Typical
3.3
2.5
Maximum
3.465
2.625
35
14
Units
V
V
mA
mA
T
ABLE
4C. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DD1
= V
DD2
= 2.5V±5%, T
A
= -40°
TO
85°C
Symbol
V
DD
V
DDx
I
DD
Parameter
Core Supply Voltage
Output Supply Voltage; NOTE 1
Power Supply Current
I
DDx
Output Supply Current; NOTE 2
NOTE 1: V
DDx
denotes V
DD1
and V
DD2
.
NOTE 2: I
DDx
denotes the sum of I
DD1
and I
DD2
.
T
ABLE
4D. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DD1
= V
DD2
= 2.5V±5%, T
A
= -40°
TO
85°C
Symbol Parameter
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
I
OZL
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
OE1, OE2
CLK
OE1, OE2
CLK
OE1, OE2
CLK
OE1, OE2
CLK
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-150
-5
1.8
0.5
5
5
Test Conditions
Minimum
2
2
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
1.3
5
150
Units
V
V
V
V
µA
µA
µA
µA
V
V
µA
µA
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output Tristate Current Low
Output Tristate Current High
I
OZH
NOTE 1: Outputs terminated with 50
Ω
to V
DDx
/2. See Parameter Measurement Information,
3.3V/2.5 Output Load Test Circuit.
8343AYI-01
www.icst.com/products/hiperclocks.html
4
REV. A JUNE 22, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8343I-01
L
OW
S
KEW
, 1-
TO
-16
LVCMOS / LVTTL F
ANOUT
B
UFFER
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
34
13
Units
V
V
mA
mA
T
ABLE
4E. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DD1
= V
DD2
= 2.5V±5%, T
A
= -40°
TO
85°C
Symbol
V
DD
V
DDx
I
DD
Parameter
Core Supply Voltage
Output Supply Voltage; NOTE 1
Power Supply Current
I
DDx
Output Supply Current; NOTE 2
NOTE 1: V
DDx
denotes V
DD1
and V
DD2
.
NOTE 2: I
DDx
denotes the sum of I
DD1
and I
DD2
.
T
ABLE
4F. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DD1
= V
DD2
= 2.5V±5%, T
A
= -40°
TO
85°C
Symbol Parameter
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
I
OZL
I
OZH
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
OE1, OE2
CLK
OE1, OE2
CLK
OE1, OE2
CLK
OE1, OE2
CLK
V
DD
= V
IN
= 2.625V
V
DD
= V
IN
= 2.625V
V
DD
= 2.625V, V
IN
= 0V
V
DD
= 2.625V, V
IN
= 0V
-150
-5
1.8
0.5
5
5
Test Conditions
Minimum
2
2
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
1.3
5
150
Units
V
V
V
V
µA
µA
µA
µA
V
V
µA
µA
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output Tristate Current Low
Output Tristate Current High
NOTE 1: Outputs terminated with 50
Ω
to V
DDx
/2. See Parameter Measurement Information, 2.5V Output Load Test Circuit.
8343AYI-01
www.icst.com/products/hiperclocks.html
5
REV. A JUNE 22, 2004