S71NS064JA0BAW003 datasheet, PDF

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S71NS064JA0BAW003: DescriptionMemory Circuit, Flash+PSRAM, CMOS, PBGA44; Categorystorage storage; File Size546KB，24 Pages; ManufacturerAMD; Websitehttp://www.amd.com; Environmental Compliance

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S71NS064JA0BAW003 Overview

Memory Circuit, Flash+PSRAM, CMOS, PBGA44

S71NS064JA0BAW003 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
package instruction	FBGA, BGA44,8X14,20
Reach Compliance Code	compliant
Maximum access time	87.5 ns
JESD-30 code	R-PBGA-B44
Memory IC Type	MEMORY CIRCUIT
Mixed memory types	FLASH+PSRAM
Number of terminals	44
Maximum operating temperature	85 °C
Minimum operating temperature	-25 °C
Package body material	PLASTIC/EPOXY
encapsulated code	FBGA
Encapsulate equivalent code	BGA44,8X14,20
Package shape	RECTANGULAR
Package form	GRID ARRAY, FINE PITCH
power supply	1.8 V
Certification status	Not Qualified
Maximum standby current	0.00006 A
Maximum slew rate	0.025 mA
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal form	BALL
Terminal pitch	0.5 mm
Terminal location	BOTTOM
Base Number Matches	1

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S71NS128JA0/S71NS064JA0

Stacked Multi-Chip Product (MCP)

128 Megabit (8 M x 16-Bit) and 64 Megabit (4 M x 16-Bit),

110 nm CMOS 1.8 Volt-only Simultaneous Read/Write,

Burst Mode Flash Memories with

16 Megabit (1M x 16-Bit) pSRAM

Data Sheet

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Publication Number

31136_00

Revision

Amendment

Issue Date

March 21, 2005

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S71NS128JA0/S71NS064JA0

31136_00_A4 March 21, 2005

A d v a n c e

I n f o r m a t i o n

Contents

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Physical Dimensions–S71NS128JA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

NLA048—48-Ball

Very Thin Fine-Pitch Ball Grid Array (FBGA)

10 x 11

mm Package ...........................................10

NLB044—44-Ball

Very Thin Fine-Pitch Ball Grid Array (FBGA)

9.2 x 8

mm Package .......................................... 11

Device History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Appendix B: Daisy Chain Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

pSRAM Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

pSRAM Device Bus Operations ............................................................................................................................................... 17

pSRAM DC Characteristics ...................................................................................................................................................... 17

pSRAM AC Characteristics ....................................................................................................................................................... 17

pSRAM Device Operation .........................................................................................................................................................18

pSRAM Read Access ...................................................................................................................................................................18

pSRAM Write Access .................................................................................................................................................................18

Configuration Register Access .................................................................................................................................................18

Revision Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Tables

Table 1

Table 2

Table 3

Table 4

Table 5

Table 6

Table 7

Daisy Chain Part for 128/16Mbit Multi-Chip Products (NLA048, 10 x 11 mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

NLA048 Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

NLA048 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Daisy Chain Part for 64/16Mbit Multi-Chip Products (NLB044, 9.2 x 8 mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

NLB044 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

NLB044 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figures

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

NLA048 Daisy Chain Layout (Top View, Balls Facing Down) .....................................................................................................14

NLB044 Daisy Chain Layout (Top View, Balls Facing Down)......................................................................................................16

Configuration Register Read Access ....................................................................................................................................................19

Configuration Register Write Access..................................................................................................................................................19

pSRAM Read Cycle 1 (WE# = VIH).....................................................................................................................................................20

pSRAM Read Cycle 2 (WE# = VIH)....................................................................................................................................................20

pSRAM Write Cycle 1 (OE# = VIH)..................................................................................................................................................... 21

pSRAM Write Cycle 2 (OE# = VIH)....................................................................................................................................................21

March 21, 2005 31136_00_A4

S71NS128JA0/S71NS064JA0

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