UT4090WPX datasheet, PDF - EEWORLD Datasheet

Standard Products

UT4090 RadHard FPGA

Advanced Data Sheet

February 21, 2001

FEATURES

q

0.35µm four-layer metal non-volatile CMOS process for

smallest die sizes

q

One-time programmable, ViaLink

TM

antifuse technology for

personalization

q

150 MHz 16-bit counters, 200 MHz datapaths, 80+ MHz

FIFOs

q

90,000 usable PLD gates

q

I/Os

- Interfaces with both 3.3 volt and 5 volt devices

- PCI compliant with 3.3V and 5V busses

- Full JTAG boundary scan

- Registered I/O cells with individually controlled clocks and

output enables

q

Radiation-hardened design; total dose irradiation testing to

MIL-STD-883 Test Method 1019

- Total-dose: 30 krad(Si)

- SEL Immune TBD

- LET

TH

(0.25) TBD

- Saturated Cross Section cm

2

per bit - TBD

q

22 dual-port RAM modules, organized in user-configurable

1,152 bit blocks

- 5ns access times, each port independently accessible

- Fast and efficient for FIFO, RAM, and ROM functions

q

100% routable with 100% utilization and complete pin-out

stability

q

Variable-grain logic cells provide high performance and

100% utilization

q

Comprehensive design tools include high quality

Verilog/VHDL synthesis

q

QuickLogic existing IP such as microcontrollers,

DRAM controllers, USART and PCI can be accessed

q

Packaged in a 208-pin Cerquad Flatpack

q

Standard Microcircuit Drawing 5962-00533

- QML Q and T compliant part

INTRODUCTION

The UT4090 RadHard Field Programmable Gate Array

(FPGA) offers 90,000 usable PLD gates of logic in

combination with Dual-Port SRAM modules. It is

fabricated on 0.35µm four-layer metal CMOS process. The

UT4090 contains 1,584 logic cells and 22 dual port RAM

modules (see Figure 1). Each RAM module has 1,152 RAM

bits, for a total of 25,344 bits. RAM modules are Dual Port

(one read port, one write port) and can be configured into

one of four modes: 64 (deep) x 18(wide), 128x9, 256x4, or

512x2 (see Figure 2). The UT4090 is available in a 208-pin

Cerquad Flatpack, allowing access to 166 bidirectional

signal I/O, 8 high drive inputs, and 5 JTAG IK/O.

Designers can cascade multiple RAM modules to increase

the depth or width allowed in single modules by connecting

corresponding address lines together and dividing the words

between modules (see Figure 3). This approach allows a

variety of address depths and word widths to be tailored to

a specific application.

Aeroflex UTMC uses QuickLogic Corporation’s licensed

ESP (Embedded Standard Products) technology for the

UT4090. QuickLogic is a pioneer in the FPGA

semiconductor and the software tools field.

IP

22

RAM

Blocks

1,584

High Speed

Logic Cells

Interface

Figure 1. UT4090 FPGA Block Diagram

WA(8:0)

WD(17:0)

WE

WCLK

MODE(1:0)

RE

D

RCLK

RA(8:0)

R

RD(17:0)

ASYNCRD

E

Q

Figure 2. UT4090 FPGA RAM Module

Figure 4. UT4090 FPGA I/O Cell

Software support for the UT4090 is available from QuickLogic.

The turnkey QuickWorks

TM

package provides the most com-

plete software solution from design entry to logic synthesis,

place and route, simulation and static timing analysis. The

QuickTools

TM

for Workstations package provides a solution

for designers who use Cadence, Exemplar, Mentor, Synopsys,

Synplicity, Viewlogic, Veribest or other third-party tools for

design entry, synthesis or simulation. Please visit Quick Log-

ic’s website at www.quicklogic.com for more information.

The UT4090 variable grain logic cell features up to 16 simulta-

neous inputs and 5 outputs within a cell that can be fragmented

into 5 independent cells. Each cell has a fan-in of 29 including

register and control lines (see Figure 5).

PRODUCT DESCRIPTION

I/O Pins

• 308 bi-directional input/output pins, PCI-compliant for 5V

and 3.3V buses (see Figure 4)

• 8 high-drive input distributed network pins

Distributed Networks

• Two array clock/control networks available to the logic cell

flip-flop clock, set and reset inputs - each driven by an input-

only pin

• Six global clock/control networks available to the logic cell

F1, flip-flop clock, set and reset inputs and the input and I/O

register clock, reset and enable inputs, as well as the output

enable control - each driven by an input-only or I/O pin, or

any logic cell output, or I/O cell feedback.

Performance

• Input + logic cell + output total delays under 12ns

WDATA

RAM

Module

(1,152 bits)

RDATA

WADDR

RADDR

RAM

Module

(1,152 bits)

WDATA

RDATA

• Data path speeds over 200 MHz

• Counter speeds over 150 MHz

• FIFO speeds over 80+ MHz

Figure 3. UT4090 FPGA Module Bits

2

QS

A1

A2

A3

A4

A5

A6

OS

OP

B1

B2

C1

C2

MP

MS

D1

D2

E1

E2

NP

NS

F1

F2

F3

F4

F5

F6

QC

QR

AZ

OZ

S

D

CK

R

NZ

QZ

FZ

Figure 5. UT4090 FPGA Logic Cell

3

I/O

VCC

I/O

GND

1

.

9

10

11

12

13

I/O

208

207 TDO

206

I/O

.

202

201 VCC

I/O

200

199 GND

198

I/O

.

188

187 VCCIO

186

I/O

.

183

182 GND

181

I/O

.

178

177 GND

176

I/O

.

166

165 VCC

I/O

164

163 GND

162

I/O

.

159

158 STM

157 TCK

156

.

148

147

146

145

144

.

135

134

133

132

131

130

129

128

127

126

.

117

116

115

114

113

.

105

I/O

GND

I/O

VCC

I/O

GND

I/O

GCLK/I

ACLK/I

VCC

GCLK/I

VCC

.

22

23

24

25

26

27

28

29

30

31

.

40

41

42

43

44

.

52

Top View

VCC

GCLK/I

VCC

ACLK/I

GCLK/I

I/O

GND

I/O

VCC

I/O

GND

I/O

VCC

I/O

I/O 53

TDI 54

55

.

I/O

.

58

GND 59

I/O 60

VCC 61

62

.

I/O

.

72

GND 73

74

.

I/O

.

77

GND 78

79

.

I/O

.

82

VCCIO 83

84

.

I/O

.

94

GND 95

I/O 96

VCC 97

98

.

I/O

.

102

TRSTB 103

TMS 104

Figure 6. UT4090 FPGA Logic 208 Pinout

4

Table 1: UT4090 208-pin Cerquad Flatpack Pinout Table

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

I/O

VCC

I/O

GND

I/O

GND

I/O

GCLK/I

ACLK/I

VCC

GCLK/I

VCC

I/O

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

I/O

VCC

I/O

GND

I/O

TDI

I/O

GND

I/O

VCC

I/O

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

I/O

GND

I/O

GND

I/O

VCCIO

I/O

GND

I/O

VCC

I/O

TRSTB

TMS

I/O

5

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

I/O

VCC

I/O

GND

I/O

GND

I/O

GCLK/I

ACLK/I

VCC

GCLK/I

VCC

I/O

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

I/O

VCC

I/O

GND

I/O

TCK

STM

I/O

GND

I/O

VCC

I/O

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

I/O

GND

I/O

GND

I/O

VCCIO

I/O

GND

I/O

VCC

I/O

TDO

I/O

Parameter Name	Attribute value
package instruction	GQFF,
Reach Compliance Code	unknown
ECCN code	3A001.A.2.C
Combined latency of CLB-Max	6.496 ns
JESD-30 code	S-CQFP-F208
length	28 mm
Configurable number of logic blocks	1584
Equivalent number of gates	90000
Number of terminals	208
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	1584 CLBS, 90000 GATES
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	GQFF
Package shape	SQUARE
Package form	FLATPACK, GUARD RING
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	3.302 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	FLAT
Terminal pitch	1.1 mm
Terminal location	QUAD
width	28 mm
Base Number Matches	1

	UT4090WPX	UT4090WPC
Description	Field Programmable Gate Array, 1584 CLBs, 90000 Gates, CMOS, CQFP208, CERAMIC, QFP-208	Field Programmable Gate Array, 1584 CLBs, 90000 Gates, CMOS, CQFP208, CERAMIC, QFP-208
package instruction	GQFF,	GQFF,
Reach Compliance Code	unknown	unknown
ECCN code	3A001.A.2.C	3A001.A.2.C
Combined latency of CLB-Max	6.496 ns	6.496 ns
JESD-30 code	S-CQFP-F208	S-CQFP-F208
length	28 mm	28 mm
Configurable number of logic blocks	1584	1584
Equivalent number of gates	90000	90000
Number of terminals	208	208
Maximum operating temperature	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C
organize	1584 CLBS, 90000 GATES	1584 CLBS, 90000 GATES
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	GQFF	GQFF
Package shape	SQUARE	SQUARE
Package form	FLATPACK, GUARD RING	FLATPACK, GUARD RING
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified	Not Qualified
Maximum seat height	3.302 mm	3.302 mm
Maximum supply voltage	3.6 V	3.6 V
Minimum supply voltage	3 V	3 V
Nominal supply voltage	3.3 V	3.3 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	MILITARY	MILITARY
Terminal form	FLAT	FLAT
Terminal pitch	1.1 mm	1.1 mm
Terminal location	QUAD	QUAD
width	28 mm	28 mm
Base Number Matches	1	1

UT4090WPX

UT4090WPX Overview

UT4090WPX Parametric

Preview

UT4090WPX Related Products

Recommended Resources