UT4090WPC datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Programmable logic devices> Programmable logic> UT4090WPC

UT4090WPC: DescriptionField Programmable Gate Array, 1584 CLBs, 90000 Gates, CMOS, CQFP208, CERAMIC, QFP-208; CategoryProgrammable logic devices Programmable logic; File Size244KB，13 Pages; ManufacturerCobham PLC

Download Datasheet Parametric Compare View All

UT4090WPC Overview

Field Programmable Gate Array, 1584 CLBs, 90000 Gates, CMOS, CQFP208, CERAMIC, QFP-208

UT4090WPC Parametric

Parameter Name	Attribute value
package instruction	GQFF,
Reach Compliance Code	unknown
ECCN code	3A001.A.2.C
Combined latency of CLB-Max	6.496 ns
JESD-30 code	S-CQFP-F208
length	28 mm
Configurable number of logic blocks	1584
Equivalent number of gates	90000
Number of terminals	208
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	1584 CLBS, 90000 GATES
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	GQFF
Package shape	SQUARE
Package form	FLATPACK, GUARD RING
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	3.302 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	FLAT
Terminal pitch	1.1 mm
Terminal location	QUAD
width	28 mm
Base Number Matches	1

Preview

Download Datasheet

View All

Standard Products

UT4090 RadHard FPGA

Advanced Data Sheet

February 21, 2001

FEATURES

0.35µm four-layer metal non-volatile CMOS process for

smallest die sizes

One-time programmable, ViaLink

antifuse technology for

personalization

150 MHz 16-bit counters, 200 MHz datapaths, 80+ MHz

FIFOs

90,000 usable PLD gates

I/Os

- Interfaces with both 3.3 volt and 5 volt devices

- PCI compliant with 3.3V and 5V busses

- Full JTAG boundary scan

- Registered I/O cells with individually controlled clocks and

output enables

Radiation-hardened design; total dose irradiation testing to

MIL-STD-883 Test Method 1019

- Total-dose: 30 krad(Si)

- SEL Immune TBD

- LET

(0.25) TBD

- Saturated Cross Section cm

per bit - TBD

22 dual-port RAM modules, organized in user-configurable

1,152 bit blocks

- 5ns access times, each port independently accessible

- Fast and efficient for FIFO, RAM, and ROM functions

100% routable with 100% utilization and complete pin-out

stability

Variable-grain logic cells provide high performance and

100% utilization

Comprehensive design tools include high quality

Verilog/VHDL synthesis

QuickLogic existing IP such as microcontrollers,

DRAM controllers, USART and PCI can be accessed

Packaged in a 208-pin Cerquad Flatpack

Standard Microcircuit Drawing 5962-00533

- QML Q and T compliant part

INTRODUCTION

The UT4090 RadHard Field Programmable Gate Array

(FPGA) offers 90,000 usable PLD gates of logic in

combination with Dual-Port SRAM modules. It is

fabricated on 0.35µm four-layer metal CMOS process. The

UT4090 contains 1,584 logic cells and 22 dual port RAM

modules (see Figure 1). Each RAM module has 1,152 RAM

bits, for a total of 25,344 bits. RAM modules are Dual Port

(one read port, one write port) and can be configured into

one of four modes: 64 (deep) x 18(wide), 128x9, 256x4, or

512x2 (see Figure 2). The UT4090 is available in a 208-pin

Cerquad Flatpack, allowing access to 166 bidirectional

signal I/O, 8 high drive inputs, and 5 JTAG IK/O.

Designers can cascade multiple RAM modules to increase

the depth or width allowed in single modules by connecting

corresponding address lines together and dividing the words

between modules (see Figure 3). This approach allows a

variety of address depths and word widths to be tailored to

a specific application.

Aeroflex UTMC uses QuickLogic Corporation’s licensed

ESP (Embedded Standard Products) technology for the

UT4090. QuickLogic is a pioneer in the FPGA

semiconductor and the software tools field.

RAM

Blocks

1,584

High Speed

Logic Cells

Interface

Figure 1. UT4090 FPGA Block Diagram

UT4090WPC Related Products

	UT4090WPC	UT4090WPX
Description	Field Programmable Gate Array, 1584 CLBs, 90000 Gates, CMOS, CQFP208, CERAMIC, QFP-208	Field Programmable Gate Array, 1584 CLBs, 90000 Gates, CMOS, CQFP208, CERAMIC, QFP-208
package instruction	GQFF,	GQFF,
Reach Compliance Code	unknown	unknown
ECCN code	3A001.A.2.C	3A001.A.2.C
Combined latency of CLB-Max	6.496 ns	6.496 ns
JESD-30 code	S-CQFP-F208	S-CQFP-F208
length	28 mm	28 mm
Configurable number of logic blocks	1584	1584
Equivalent number of gates	90000	90000
Number of terminals	208	208
Maximum operating temperature	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C
organize	1584 CLBS, 90000 GATES	1584 CLBS, 90000 GATES
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	GQFF	GQFF
Package shape	SQUARE	SQUARE
Package form	FLATPACK, GUARD RING	FLATPACK, GUARD RING
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified	Not Qualified
Maximum seat height	3.302 mm	3.302 mm
Maximum supply voltage	3.6 V	3.6 V
Minimum supply voltage	3 V	3 V
Nominal supply voltage	3.3 V	3.3 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	MILITARY	MILITARY
Terminal form	FLAT	FLAT
Terminal pitch	1.1 mm	1.1 mm
Terminal location	QUAD	QUAD
width	28 mm	28 mm
Base Number Matches	1	1

Recommended Resources

OTL power amplifier circuit in transistor radio a

Delay light circuit using digital circuit (1)

Excellent performance motor proportional drive circuit b

Same-line telephone switching circuit (2)

High efficiency emergency light power circuit

Stereo Balance Indicator Circuit

Several parameter issues of audio playback equipment: [b][font=宋体][color=#0000ff]【Ask if you don't understand】 I've seen some audio playback devices with the following parameter questions [/color][/font][/b][b][font=宋体][color=#0000ff]【1】The audio respons...; shaorc Analog electronics

MSP430 and Audio: ...; 火辣西米秀 Microcontroller MCU

I want to switch careers to Linux software, and I found a job with only one day off a week. Should I take it?: The poster works in Wuhan and changed his career to Linux software. A few days ago, he interviewed a company that makes medical equipment. After two interviews, it seems that he passed. At present, he...; Nubility Talking

[NXP Rapid IoT Review] + Use offline IDE to build an application that displays sensor information: Using offline IDE development can be more flexible. This time, the temperature and humidity, light intensity, air quality, power and charging status are collected and displayed on the screen.The opera...; manhuami2007 RF/Wirelessly

Could you please tell me what kind of circuit can output such a voltage?: V1 is a voltage that changes from 1 to 20V, Vin is the input voltage, and Vout is the output voltage. Can an amplifier be used to control the Vout output through Vin so that Vout = Vin* total number o...; littleshrimp Power technology

4412 Development Board Qt Timer - Experimental Steps and Partial Code: Experimental goal: realize the timer function, and click the dot button to print out the current time.The classes used are QTimer and QTime. QTimer is a timer class, equivalent to a stopwatch, and QTi...; 遥寄山川 ARM Technology

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components