DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD16878
MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT
DESCRIPTION
The
µ
PD16878 is a monolithic quad H bridge driver IC that employs a CMOS control circuit and a MOS FET
output circuit. Because it uses MOS FETs in its output stage, this driver IC consumes less power than conventional
driver ICs that use bipolar transistors.
Because the
µ
PD16878 controls a motor by inputting serial data, its package has been shrunk and the number of
pins reduced. As a result, the performance of the application set can be improved and the size of the set has been
reduced.
The
µ
PD16878 employs a current-controlled 64-step micro step driving method that drives stepper motor with low
vibration.
The
µ
PD16878 is housed in a 38-pin plastic shrink SOP to contribute to the miniaturization of the application set.
The
µ
PD16878 can simultaneously drive two stepper motors and is ideal for the mechanisms of camcorders.
FEATURES
•
Four H bridge circuits employing power MOS FETs
•
Current-controlled 64-step micro step driving
•
Motor control by serial data (8 bytes x 8 bits) (original oscillation: 4-MHz input)
Data is input with the LSB first.
EVR reference setting voltage: 100 to 250 mV (@V
REF
= 250 mV) ... 4-bit data input (10-mV step)
Chopping frequency: 32 to 124 kHz ... 5-bit data input (4-kHz step)
Original oscillation division or internal oscillation selectable
Number of pulses in 1 V
D
: 0 to 126 pulses ... 6 bits + 2-bit data input (2 pulses/step)
Step cycle: 0.25 to 8191.75
µ
s ... 15-bit data input (0.25-
µ
s step)
•
3-V power supply. Minimum operating voltage: 2.7 V (MIN.)
•
Low current consumption I
DD
: 3.0 mA (MAX.), I
DD (RESET)
: 100
µ
A (MAX.), I
MO(RESET)
: 1.0
µ
A (MAX.)
•
38-pin plastic shrink SOP (7.62 mm (300))
ORDERING INFORMATION
Part number
Package
38-pin plastic shrink SOP (7.62 mm (300))
µ
PD16878GS-BGG
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
S15974EJ1V0DS00 (1st edition)
Date Published February 2002 N CP(K)
Printed in Japan
©
2002
µ
PD16878
1. PIN FUNCTIONS
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Symbol
LGND
C
OSC
FIL
A
FIL
B
FIL
C
FIL
D
V
REF
V
DD
V
M3
D
2
FB
D
D
1
V
M4
C
2
FB
C
C
1
EXP0
EXP1
EXP2
PGND
EXP3
EXT
α
V
M1
A
1
FB
A
A
2
V
M2
B
1
FB
B
B
2
EXT
β
V
D
LATCH
SDATA
SCLK
OSC
IN
OSC
OUT
RESET
Control circuit GND pin
Chopping capacitor connection pin
Function
α
1-ch filter capacitor connection pin (1000 pF TYP.)
α
2-ch filter capacitor connection pin (1000 pF TYP.)
β
1-ch filter capacitor connection pin (1000 pF TYP.)
β
2-ch filter capacitor connection pin (1000 pF TYP.)
Reference voltage input pin (250 mV TYP.)
Control circuit supply voltage input pin
Output circuit supply voltage input pin
β
2-ch output pin
β
2-ch sense resistor connection pin
β
2-ch output pin
Output circuit supply voltage connection pin
β
1-ch output pin
β
1-ch sense resistor connection pin
β
1-ch output pin
Output monitor pin (open drain)
Output monitor pin (open drain)
Output monitor pin (open drain)
Power circuit GND pin
Output monitor pin (open drain)
Logic circuit monitor pin
Output circuit supply voltage input pin
α
1-ch output pin
α
1-ch sense resistor connection pin
α
1-ch output pin
Output circuit supply voltage input pin
α
2-ch output pin
α
2-ch sense resistor connection pin
α
2-ch output pin
Logic circuit monitor pin
Video sync signal input pin
Latch signal input pin
Serial data input pin
Serial clock input pin
Original oscillation input pin (4 MHz TYP.)
Original oscillation output pin
Reset signal output pin
4
Data Sheet S15974EJ1V0DS