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74LVX00MX_NL

Description
Low Voltage Quad 2-Input NAND Gate
Categorylogic    logic   
File Size84KB,6 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Environmental Compliance
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74LVX00MX_NL Overview

Low Voltage Quad 2-Input NAND Gate

74LVX00MX_NL Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerFairchild
Parts packaging codeSOIC
package instructionSOP, SOP14,.25
Contacts14
Reach Compliance Codecompliant
seriesLV/LV-A/LVX/H
JESD-30 codeR-PDSO-G14
JESD-609 codee3
length8.6235 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeNAND GATE
MaximumI(ol)0.004 A
Humidity sensitivity level1
Number of functions4
Number of entries2
Number of terminals14
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP14,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE
method of packingTAPE AND REEL
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Prop。Delay @ Nom-Sup11 ns
propagation delay (tpd)16 ns
Certification statusNot Qualified
Schmitt triggerNO
Maximum seat height1.753 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)2.7 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width3.9 mm
Base Number Matches1

74LVX00MX_NL Related Products

74LVX00MX_NL 74LVX00 74LVX00M 74LVX00MTCX_NL 74LVX00SJ
Description Low Voltage Quad 2-Input NAND Gate Low Voltage Quad 2-Input NAND Gate Low Voltage Quad 2-Input NAND Gate Low Voltage Quad 2-Input NAND Gate Low Voltage Quad 2-Input NAND Gate
Is it Rohs certified? conform to - conform to conform to conform to
Maker Fairchild - Fairchild Fairchild Fairchild
Parts packaging code SOIC - SOIC TSSOP SOIC
package instruction SOP, SOP14,.25 - SOP, SOP14,.25 TSSOP, TSSOP14,.25 SOP, SOP14,.3
Contacts 14 - 14 14 14
Reach Compliance Code compliant - compliant compliant compliant
series LV/LV-A/LVX/H - LV/LV-A/LVX/H LV/LV-A/LVX/H LV/LV-A/LVX/H
JESD-30 code R-PDSO-G14 - R-PDSO-G14 R-PDSO-G14 R-PDSO-G14
JESD-609 code e3 - e3 e3 e3
length 8.6235 mm - 8.6235 mm 5 mm 10.2 mm
Load capacitance (CL) 50 pF - 50 pF 50 pF 50 pF
Logic integrated circuit type NAND GATE - NAND GATE NAND GATE NAND GATE
MaximumI(ol) 0.004 A - 0.004 A 0.004 A 0.004 A
Humidity sensitivity level 1 - 1 1 1
Number of functions 4 - 4 4 4
Number of entries 2 - 2 2 2
Number of terminals 14 - 14 14 14
Maximum operating temperature 85 °C - 85 °C 85 °C 85 °C
Minimum operating temperature -40 °C - -40 °C -40 °C -40 °C
Package body material PLASTIC/EPOXY - PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code SOP - SOP TSSOP SOP
Encapsulate equivalent code SOP14,.25 - SOP14,.25 TSSOP14,.25 SOP14,.3
Package shape RECTANGULAR - RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE - SMALL OUTLINE SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE
Peak Reflow Temperature (Celsius) 260 - 260 260 260
power supply 3.3 V - 3.3 V 3.3 V 3.3 V
Prop。Delay @ Nom-Sup 11 ns - 11 ns 11 ns 11 ns
propagation delay (tpd) 16 ns - 16 ns 16 ns 16 ns
Certification status Not Qualified - Not Qualified Not Qualified Not Qualified
Schmitt trigger NO - NO NO NO
Maximum seat height 1.753 mm - 1.753 mm 1.2 mm 2.1 mm
Maximum supply voltage (Vsup) 3.6 V - 3.6 V 3.6 V 3.6 V
Minimum supply voltage (Vsup) 2 V - 2 V 2 V 2 V
Nominal supply voltage (Vsup) 2.7 V - 2.7 V 2.7 V 2.7 V
surface mount YES - YES YES YES
technology CMOS - CMOS CMOS CMOS
Temperature level INDUSTRIAL - INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal surface Matte Tin (Sn) - Matte Tin (Sn) Matte Tin (Sn) MATTE TIN
Terminal form GULL WING - GULL WING GULL WING GULL WING
Terminal pitch 1.27 mm - 1.27 mm 0.65 mm 1.27 mm
Terminal location DUAL - DUAL DUAL DUAL
Maximum time at peak reflow temperature NOT SPECIFIED - NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
width 3.9 mm - 3.9 mm 4.4 mm 5.3 mm
Base Number Matches 1 - 1 1 1
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