INTEGRATED CIRCUITS
74LVC125
Quad buffer/line driver; 3-State
Product specification
Supersedes data of February 1996
IC24 Data Handbook
1997 Mar 18
Philips
Semiconductors
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-State
74LVC125
FEATURES
•
Wide supply voltage range of 1.2 to 3.6 V
•
In accordance with JEDEC standard no. 8-1A
•
Inputs accept voltages up to 5.5 V
•
CMOS lower power consumption
•
Direct interface with TTL levels
•
Output drive capability 50
W
transmission lines at 85°C
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25°C; t
r
= t
f
≤
2.5 ns
SYMBOL
t
PHL
/t
PLH
C
I
C
PD
PARAMETER
Propagation delay
nA to nY
Input capacitance
Power dissipation capacitance per buffer
DESCRIPTION
The 74LVC125 is a high performance, low-power, low-voltage
Si-gate CMOS device and superior to most advanced CMOS
compatible TTL families.
The 74LVC125 consists of four non-inverting buffers/line drivers with
3-State outputs. The 3-State outputs (nY) are controlled by the
output enable input (nOE). A HIGH at nOE causes the outputs to
assume a high impedance OFF-state.
CONDITIONS
C
L
= 15 pF;
V
CC
= 3.3 V
Notes 1 and 2
TYPICAL
3.5
5.0
22
UNIT
ns
pF
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW)
P
D
= C
PD
×
V
CC2
×
f
i
+Σ (C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
Σ
(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
ORDERING INFORMATION
PACKAGES
14-Pin Plastic SO
14-Pin Plastic SSOP Type II
14-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74LVC125 D
74LVC125 DB
74LVC125 PW
NORTH AMERICA
74LVC125 D
74LVC125 DB
74LVC125PW DH
PKG. DWG. #
SOT108-1
SOT337-1
SOT402-1
PIN CONFIGURATION
1OE
1A
1Y
2OE
2A
2Y
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
4OE
4A
4Y
3OE
3A
3Y
LOGIC SYMBOL
2
1A
1Y
3
1
5
1OE
2A
2Y
6
4
9
2OE
3A
3Y
8
10
3OE
4A
4Y
11
SV00455
12
PIN DESCRIPTION
PIN
NUMBER
1, 4, 10, 13
2, 5, 9, 12
3, 6, 8, 11
7
14
SYMBOL
1OE – 4OE
1A – 4A
1Y – 4Y
GND
V
CC
NAME AND FUNCTION
Data enable inputs (active LOW)
Data inputs
Data Outputs
Ground (0 V)
Positive supply voltage
13
4OE
SV00456
1997 Mar 18
2
853–1951 17865
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-State
74LVC125
FUNCTION TABLE
INPUTS
nOE
L
L
H
NOTES:
H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high impedance OFF-state
nA
L
H
X
OUTPUT
nY
L
H
Z
LOGIC SYMBOL (IEEE/IEC)
2
1
3
1
EN1
5
6
4
9
8
10
12
11
13
SV00457
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
CC
V
I
V
I/O
V
O
T
amb
t
r
, t
f
PARAMETER
DC supply voltage (for max. speed performance)
DC supply voltage (for low-voltage applications)
DC input voltage range
DC input voltage range for I/Os
DC output voltage range
Operating free-air temperature range
Input rise and fall times
V
CC
= 1.2 to 2.7V
V
CC
= 2.7 to 3.6V
CONDITIONS
LIMITS
MIN
2.7
1.2
0
0
0
–40
0
0
MAX
3.6
3.6
5.5
V
CC
V
CC
+85
20
10
UNIT
V
V
V
V
V
°C
ns/V
ABSOLUTE MAXIMUM RATINGS
1
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0 V).
SYMBOL
V
CC
I
IK
V
I
V
I/O
I
OK
V
OUT
I
OUT
I
GND
, I
CC
T
stg
P
TOT
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
DC input voltage range for I/Os
DC output diode current
DC output voltage
DC output source or sink current
DC V
CC
or GND current
Storage temperature range
Power dissipation per package
– plastic mini-pack (SO)
– plastic shrink mini-pack (SSOP and TSSOP)
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
V
O
uV
CC
or V
O
t
0
Note 2
V
O
= 0 to V
CC
V
I
t
0
Note 2
CONDITIONS
RATING
–0.5 to +6.5
–50
–0.5 to +5.5
–0.5 to V
CC
+0.5
"50
–0.5 to V
CC
+0.5
"50
"100
–60 to +150
500
500
UNIT
V
mA
V
V
mA
V
mA
mA
°C
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1997 Mar 18
3
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-State
74LVC125
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
MIN
V
IH
HIGH level Input voltage
V
CC
= 1.2V
V
CC
= 2.7 to 3.6V
LOW level Input voltage
V
CC
= 1.2V
V
CC
= 2.7 to 3.6V
V
CC
= 2.7V; V
I
= V
IH
or V
IL
; I
O
= –12mA
V
O
OH
HIGH level output voltage
V
CC
= 3.0V; V
I
= V
IH
or V
IL
; I
O
= –100µA
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= –12mA
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= –24mA
V
CC
= 2.7V; V
I
= V
IH
or V
IL
; I
O
= 12mA
V
OL
LOW level output voltage
V
CC
= 3.0V; V
I
= V
IH
or V
IL
; I
O
= 100µA
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= 24mA
I
I
I
IHZ
/I
ILZ
I
OZ
I
CC
∆I
CC
Input leakage current
Input current for common I/O pins
3-State output OFF-state current
Quiescent supply current
Additional quiescent supply current per
input pin
V
CC
= 3 6V; V
I
= 5 5V or GND
3.6V;
5.5V
V
CC
= 3.6V; V
I
= V
CC
or GND
V
CC
= 3.6V; V
I
= V
IH
or V
IL
; V
O
= V
CC
or GND
V
CC
= 3.6V; V
I
= V
CC
or GND; I
O
= 0
V
CC
= 2.7V to 3.6V; V
I
= V
CC
–0.6V; I
O
= 0
Not for I/O pins
"0.1
"0
1
"0.1
0.1
0.1
5
GND
V
CC
*0.5
V
CC
*0.2
V
CC
*0.6
V
CC
*1.0
0.40
0.20
0.55
"5
"15
"10
20
500
µA
µA
µA
µA
µA
V
V
CC
V
V
CC
2.0
GND
V
0.8
TYP
1
MAX
V
UNIT
V
IL
NOTE:
1. All typical values are at V
CC
= 3.3V and T
amb
= 25°C.
1997 Mar 18
4
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-State
74LVC125
AC CHARACTERISTICS
GND = 0 V; t
r
= t
f
= 2.5 ns; C
L
= 50 pF; R
L
= 500W; T
amb
= –40_C to +85_C.
LIMITS
SYMBOL
PARAMETER
WAVEFORM
V
CC
= 3.3V
±0.3V
MIN
t
PHL
t
PLH
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation delay
nA to nY
3-state output enable
time nOE to nY
3-state output disable
time nOE to nY
Figure 1, 3
Figure 2, 3
Figure 2, 3
TYP
1
3.5
3.8
3.3
MAX
6.5
7.0
5.5
MIN
V
CC
= 2.7V
TYP
3.9
4.4
4.0
MAX
7.0
8.0
6.5
V
CC
= 1.2V
TYP
ns
ns
ns
UNIT
NOTE:
1. These typical values are at V
CC
= 3.3V and T
amb
= 25°C.
AC WAVEFORMS
V
M
= 1.5 V at V
CC
w
2.7 V
V
M
= 0.5
×
V
CC
at V
CC
< 2.7 V
V
OL
and V
OH
are the typical output voltage drop that occur with the
output load.
V
X
= V
OL
+ 0.3 V at V
CC
≥
2.7 V;
V
X
= V
OL
+ 0.1
×
V
CC
at V
CC
< 2.7 V;
V
Y
= V
OH
– 0.3 V at V
CC
≥
2.7 V;
V
Y
= V
OH
– 0.1
×
V
CC
at V
CC
< 2.7 V.
V
l
nA INPUT
GND
t PHL
V OH
nY OUTPUT
V OL
VM
t PLH
VM
TEST CIRCUIT
V
CC
S
1
2
<
V
CC
Open
GND
PULSE
GENERATOR
V
I
D.U.T.
R
T
V
O
500Ω
C
L
50pF
500Ω
Test
V
CC
t
2.7V
2.7V – 3.6V
V
I
V
CC
2.7V
t
PLH
/t
PHL
t
PLZ
/t
PZL
t
PHZ
/t
PZH
S
1
Open
2
<
V
CC
GND
SY00003
Figure 3. Load circuitry for switching times.
SV00459
Figure 1. Input (nA) to output (nY) propagation delays.
VI
nOE Input
GND
tPLZ
VCC
OUTPUT
LOW-to-OFF
OFF-to-LOW
VOL
tPHZ
VOH
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
GND
outputs
enabled
VY
VM
outputs
disabled
outputs
enabled
tPZL
VM
VX
tPZH
VM
SV00458
Figure 2. 3-State enable and disable times.
1997 Mar 18
5
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