IS61VF51218A-7.5B2 datasheet, PDF

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IS61VF51218A-7.5B2: DescriptionCache SRAM, 512KX18, 7.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119; Categorystorage storage; File Size630KB，32 Pages; ManufacturerIntegrated Silicon Solution ( ISSI )

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IS61VF51218A-7.5B2 Overview

Cache SRAM, 512KX18, 7.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119

IS61VF51218A-7.5B2 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Integrated Silicon Solution ( ISSI )
Parts packaging code	BGA
package instruction	BGA, BGA119,7X17,50
Contacts	119
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	7.5 ns
Other features	FLOW-THROUGH ARCHITECTURE
Maximum clock frequency (fCLK)	117 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B119
JESD-609 code	e0
length	22 mm
memory density	9437184 bit
Memory IC Type	CACHE SRAM
memory width	18
Humidity sensitivity level	3
Number of functions	1
Number of terminals	119
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512KX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA119,7X17,50
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2.5 V
Certification status	Not Qualified
Maximum seat height	3.5 mm
Maximum standby current	0.045 A
Minimum standby current	2.38 V
Maximum slew rate	0.175 mA
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm

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IS61LF25636A IS61VF25636A IS64LF25636A

IS61LF51218A IS61VF51218A

256K x 36, 512K x 18

9 Mb SYNCHRONOUS FLOW-THROUGH

AUGUST 2009

STATIC RAM

FEATURES

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Burst sequence control using MODE input

• Three chip enable option for simple depth expan-

sion and address pipelining

• Common data inputs and data outputs

• Auto Power-down during deselect

• Single cycle deselect

• Snooze MODE for reduced-power standby

• JTAG Boundary Scan for PBGA package

• Power Supply

LF: V

3.3V + 5%,

ddq

3.3V/2.5V + 5%

VF: V

2.5V + 5%,

ddq

2.5V + 5%

• JEDEC 100-Pin TQFP, 119-pin PBGA, and 165-

pin PBGA packages

• Lead-free available

• Automotive temperature available

DESCRIPTION

The

ISSI

IS61LF/VF25636A, IS64LF25636A and IS61LF/

VF51218A are high-speed, low-power synchronous

static RAMs designed to provide burstable, high-performance

memory for communication and networking applications.

The IS61LF/VF25636A and IS64LF25636A are organized

as 262,144 words by 36 bits. The IS61LF/VF51218A is

organized as 524,288 words by 18 bits. Fabricated with

ISSI

's advanced CMOS technology, the device integrates

a 2-bit burst counter, high-speed SRAM core, and high-

drive capability outputs into a single monolithic circuit. All

synchronous inputs pass through registers controlled by

a positive-edge-triggered single clock input.

Write cycles are internally self-timed and are initiated by the

rising edge of the clock input. Write cycles can be one to

four bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be written.

Byte write operation is performed by using byte write en-

able (BWE) input combined with one or more individual

byte write signals (BWx). In addition, Global Write (GW)

is available for writing all bytes at one time, regardless of

the byte write controls.

Bursts can be initiated with either ADSP (Address Status

Processor) or ADSC (Address Status Cache Controller)

input pins. Subsequent burst addresses can be gener-

ated internally and controlled by the

ADV

(burst address

advance) input pin.

The mode pin is used to select the burst sequence order,

Linear burst is achieved when this pin is tied LOW. Inter-

leave burst is achieved when this pin is tied HIGH or left

floating.

FAST ACCESS TIME

Symbol

Parameter

Clock Access Time

Cycle Time

Frequency

-6.5

6.5

7.5

133

-7.5

7.5

8.5

117

Units

MHz

notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-

est version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc.

Rev. F

07/22/09

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