AS7C25512PFD32A-166TQCN datasheet, PDF

Datasheet> All Categories > storage> storage> AS7C25512PFD32A-166TQCN

AS7C25512PFD32A-166TQCN: DescriptionStandard SRAM, 512KX32, 3.5ns, CMOS, PQFP100, 14 X 20 MM, LEAD FREE, TQFP-100; Categorystorage storage; File Size510KB，19 Pages; ManufacturerALSC [Alliance Semiconductor Corporation]; Environmental Compliance

Download Datasheet Parametric View All

AS7C25512PFD32A-166TQCN Overview

Standard SRAM, 512KX32, 3.5ns, CMOS, PQFP100, 14 X 20 MM, LEAD FREE, TQFP-100

AS7C25512PFD32A-166TQCN Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Parts packaging code	QFP
package instruction	LQFP, QFP100,.63X.87
Contacts	100
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Maximum access time	3.5 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	166 MHz
I/O type	COMMON
JESD-30 code	R-PQFP-G100
JESD-609 code	e3
length	20 mm
memory density	16777216 bit
Memory IC Type	STANDARD SRAM
memory width	32
Number of functions	1
Number of terminals	100
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512KX32
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Encapsulate equivalent code	QFP100,.63X.87
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	245
power supply	2.5 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum standby current	0.04 A
Minimum standby current	2.38 V
Maximum slew rate	0.29 mA
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	MATTE TIN
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	14 mm
Base Number Matches	1

Preview

Download Datasheet

View All

February 2005

AS7C25512PFD32A

AS7C25512PFD36A

2.5V 512K

32/36 pipelined burst synchronous SRAM

Features

•

Organization: 524,288 words × 32 or 36 bits

Fast clock speeds to 166 MHz

Fast clock to data access: 3.5/3.8 ns

Fast OE access time: 3.5/3.8 ns

Fully synchronous register-to-register operation

Double-cycle deselect

Asynchronous output enable control

Available in 100-pin TQFP package

•

Individual byte write and global write

Multiple chip enables for easy expansion

2.5V core power supply

Linear or interleaved burst control

Snooze mode for reduced power-standby

Common data inputs and data outputs

Logic block diagram

LBO

CLK

ADV

ADSC

ADSP

A[18:0]

CLK

CLR

Address

CLK

Burst logic

512K × 32/36

Memory

array

GWE

BWE

Byte write

registers

CLK

Byte write

registers

CLK

Byte write

registers

CLK

Byte write

registers

CLK

Enable

CLK

Power

down

Enable

delay

CLK

36/32

CE0

CE1

CE2

Output

registers

CLK

Input

registers

CLK

36/32

DQ[a:d]

Selection guide

Minimum cycle time

Maximum clock frequency

Maximum clock access time

Maximum operating current

Maximum standby current

Maximum CMOS standby current (DC)

-166

166

3.5

290

-133

7.5

133

3.8

270

Units

MHz

2/10/05, v. 1.2

Alliance Semiconductor

1 of 19

Recommended Resources

Pure-sounding tube amplifier

Gamma ray measurement circuit

Bi-phase output sine wave generator circuit diagram

555 program trigger and long delay circuit

Application wiring diagram of TX-KD301 (driver)

DMAl0 rectifier module function diagram

Ruan Gong's MCU programming experience: how to make stable MCU programs and host computer programs to prevent jamming, js and other experiences; Ruan Ding...: Ruan Gong's MCU Programming Experience Collection V2.1: How to Make Stable MCU Programs, Ruan Dingyuan:================================================== =================The problem of 0.99999 being ...; net2uizoo stm32/stm8

[NUCLEO-WL55JC2 Evaluation 3] Building the NUCLEO-WL55JC2 MDK development and testing environment: [i=s]This post was last edited by nich20xx on 2020-7-3 22:50[/i] # 1 Introduction After having a systematic understanding of NUCLEO-WL55JC2, I started running the sample code of NUCLEO-WL55JC2. Since ...; nich20xx Special Edition for Assessment Centres

Feiling domestic chip series dry goods | A40i development board PWM application notes fully disclosed: This article explains the application of PWM on the domestic A40i development board. This article is mainly applicable to the Feiling OKA40i platform Linux3.10.65 operating system. Other arm platforms...; 小螃蟹呀 ARM Technology

What are the advantages of WiMi-net wireless ad hoc network communication solution?: At present, many manufacturers have their own wireless self-organizing network solutions, and each solution cannot communicate with each other. Therefore, it is very important for users to choose a pr...; chenjingjing RF/Wirelessly

Analog Circuit Experiment Instructions: E-book [;)] http://www.pcbbbs.com/showerr.asp?BoardID=4ErrCodes=54action=%B2%E9%BF%B4%CE%C4%BC%FE [code language="J#"] [/code]...; fighting Analog electronics

Large Capacity Voice Recorder SOPC Design and Matlab Simulation.pdf: Large Capacity Voice Recorder SOPC Design and Matlab Simulation.pdf...; zxopenljx EE_FPGA Learning Park

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components