A32200DXV-CQC datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > A32200DXV-CQC

Preview

A32200DXV-CQC: DescriptionIntegrator Series FPGAs: 1200XL and 3200DX Families; File Size604KB，84 Pages; ManufacturerActel; Websitehttp://www.actel.com/

Download Datasheet View All

A32200DXV-CQC Overview

Integrator Series FPGAs: 1200XL and 3200DX Families

Preview

Download Datasheet

View All

Discontinued – v3.0

v3.0

Integrator Series FPGAs:

1200XL and 3200DX Families

F ea t u re s

H ig h C a p ac it y

G e n e ra l D es c ri p t i o n

•

2,500 to 30,000 Logic Gates

Up to 3Kbits Configurable Dual-Port SRAM

Fast Wide-Decode Circuitry

Up to 250 User-Programmable I/O Pins

225 MHz Performance

5 ns Dual-Port SRAM Access

100 MHz FIFOs

7.5 ns 35-Bit Address Decode

H ig h P e r f o r m a nc e

Actel’s Integrator Series FPGAs are the first programmable

logic devices optimized for high-speed system logic

integration. Based on Actel’s proprietary antifuse

technology and 0.6-micron double metal CMOS process,

Integrator Series devices offer a fine-grained, register-rich

architecture with embedded dual-port SRAM and

wide-decode circuitry.

Integrator Series’ 3200DX and 1200XL families were

designed to integrate system logic which is typically

implemented in multiple CPLDs, PALs, and FPGAs. These

devices provide the features and performance required for

today’s complex, high-speed digital logic systems. The

3200DX family offers fast dual-port SRAM for implementing

FIFOs, LIFOs, and temporary data storage. The large

number of storage elements can efficiently address

applications requiring wide datapath manipulation and

transformation functions such as telecommunications,

networking, and DSP.

E a s e - of -I n t e g r a t i o n

• Synthesis-Friendly Architecture Supports ASIC Design

Methodologies.

• 95–100% Device Utilization using Automatic

Place-and-Route Tools.

• Deterministic, User-Controllable Timing Via Timing

Driven Software Tools with Up To 100% Pin Fixing.

• IEEE Standard 1149.1 (JTAG) Boundary Scan Testing.

In t eg r a to r S e ri e s P ro d u ct P r of i l e F a m i l y

1200XL

Device

A1225XL

2,500

N/A

231

220

N/A

231

A1240XL

4,000

N/A

348

336

N/A

348

104

A1280XL

8,000

N/A

624

608

N/A

624

140

3200DX

A3265DX

6,500

N/A

510

475

N/A

510

126

PL84

PQ100

PQ160

TQ176

A32100DX

10,000

2,048

700

662

700

152

Yes

PL84

PQ160

PQ208

TQ176

CQ84

A32140DX

14,000

N/A

954

912

N/A

954

176

Yes

PL84

PQ160

PQ208

TQ176

CQ256

A32200DX

20,000

2,560

1,230

1,184

1,230

202

Yes

PQ208

RQ208

RQ240

CQ208

CQ256

A32300DX

30,000

3,072

1,888

1,833

1,888

250

Yes

RQ208

RQ240

CQ256

Capacity

Logic Gates

SRAM Bits

Sequential

Combinatorial

Decode

Logic Modules

SRAM Modules

(64x4 or 32x8)

Dedicated Flip-Flops

Clocks

User I/O

(Maximum)

JTAG

Packages

PL84

PQ100

VQ100

PG100

PL84 PQ100

PQ144

TQ176

PG132

PL84

PQ160 PQ208

TQ176

PG176 CQ172

Note:

Logic gate capacity does not include SRAM bits as logic.

February 2001

Recommended Resources

About star-delta step-down start plc ladder diagram circuit diagram

Automatic power shut-off circuit

Two-wire circuit diagram B

Use TWH8751 to make an inverter power supply

555 reading kiosk automatic lighting circuit

555 traffic intersection traffic light automatic controller circuit (1)

[Bluesun AB32VG1 RISC-V board "meets" RTT] + unpacking and environmental installation: [i=s]This post was last edited by xiyue521 on 2021-4-30 22:58[/i]1. The AB32VG1 development board is based on the high - configuration chip AB5301A based on the RISC-V architecture launched by Bluetru...; xiyue521 Domestic Chip Exchange

Analog electronics elective test + DC and AC parameters: https://training.eeworld.com.cn/TI/video/12740, today I watched the series of sessions of analog and digital electronics elective course, AC and DC competition numbers, and understood many things that...; jean1 TI Technology Forum

The ADC example of the underlying driver code of esp32 is added to my own project and compiled unsuccessfully: [i=s]This post was last edited by amarelo on 2022-4-22 00:01[/i]Hello everyone, I would like to ask a question. When I was programming, I wanted to add the ADC example of the underlying driver code of...; amarelo Programming Basics

[Evaluation of EVAL-M3-TS6-665PN development board] Hardware introduction and features: This content is originally created by EEWORLD forum user xiyue521 . If you want to reprint or use it for commercial purposes, you must obtain the author's consent and indicate the sourceFirst, let's i...; xiyue521 Power technology

Read the good book "Electronic Engineer Self-study Handbook" - First Look: [i=s] This post was last edited by Lazy Cat Love Flying on 2021-8-2 15:24[/i]First meetingSince I got an e-book reader, I haven't bought a paper book for more than half a year. I took advantage of thi...; 懒猫爱飞 Analog electronics

Can anyone confirm what device this is? Thanks!: Can anyone confirm what device this is? Thanks!...; wanhui2 Power technology

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components