80C154/83C154
CMOS 0 to 36 MHz Single Chip 8–bit Microcontroller
Description
TEMIC’s 80C154 and 83C154 are high performance
CMOS single chip
µC.
The 83C154 retains all the
features of the 80C52 with extended ROM capacity (16
K bytes), 256 bytes of RAM, 32 I/O lines, a 6-source
2-level interrupts, a full duplex serial port, an on-chip
oscillator and clock circuits, three 16 bit timers with extra
features : 32 bit timer and watchdog functions. Timer 0
and 1 can be configured by program to implement a 32 bit
timer. The watchdog function can be activated either with
timer 0 or timer 1 or both together (32 bit timer).
In addition, the 83C154 has 2 software-selectable modes
of reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the RAM is saved, and the timers, the serial port and the
interrupt system continue to function. In the power down
mode the RAM is saved and the timers, serial port and
interrupt continue to function when driven by external
clocks. In addition as for the TEMIC 80C51/80C52, the
stop clock mode is also available.
The 80C154 is identical to the 83C154 except that it has
no on-chip ROM. TEMIC’s 80C154 and 83C154 are
manufactured using SCMOS process which allows them
to run from 0 up to 36 MHz with Vcc = 5 V.
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80C154 : ROMless version of the 83C154µ
80C154/83C154-12 : 0 to 12 MHz
80C154/83C154-16 : 0 to 16 MHz
80C154/83C154-20 : 0 to 20 MHz
80C154/83C154-25 : 0 to 25 MHz
80C154/83C154-30 : 0 to 30 MHz
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80C154/83C154-36 : 0 to 36 MHz
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80C154/83C154-L16 : Low power version
VCC : 2.7-5.5 V Freq : 0-16 MHz
For other speed and temperature range availability please consult your
sales office.
Features
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Power control modes
256 bytes of RAM
16 Kbytes of ROM (83C154)
32 Programmable I/O lines (programmable impedance)
Three 16 bit timer/counters (including watchdog and 32 bit
timer)
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64 K program memory space
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64 K data memory space
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Fully static design
0.8µ CMOS process
Boolean processor
6 interrupt sources
Programmable serial port
Temperature range : commercial, industrial, automotive,
military
Optional
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Secret ROM : Encryption
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Secret TAG : Identification number
MATRA MHS
Rev.F (14 Jan. 97)
1
80C154/83C154
Interface
Figure 1. Block Diagram
2
MATRA MHS
Rev.F (14 Jan. 97)
80C154/83C154
Figure 2. Pin Configuration
P1.1/T2EX
P0.0/A0
P0.1/A1
P0.2/A2
P0.3/A3
P1.0/T2
P1.5
P1.6
VCC
P1.4
P1.3
P1.2
NC
P0.4/A4
P0.5/A5
P0.6/A6
P0.7/A7
EA
80C154/83C154
P1.7
RST
RxD/P3.0
NC
TxD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
80C154/83C154
NC
ALE
PSEN
P2.7/A14
P2.6/A13
P2.5/A12
P
11
/T2EX
DIL
P
14
P
13
P
12
LCC
P
10
/T2
A1/P
01
A2/P
02
A3/P
03
A0/P
0
NC
V
CC
P
15
P
16
P
17
RST
RxD/P
30
NC
TxD/P
31
INT0/P
32
INT1/P
33
T0/P
34
T1/P
35
P
04
/A4
P
05
/A5
P
06
/A6
P
07
/A7
EA
80C154/83C154
NC
ALE
PSEN
P
27
/A15
P
26
/A14
P
25
/A13
WR/P
36
RD/P
37
P
23
/A11
P
20
/A8
P
21
/A9
P
22
/A10
Flat Pack
Diagrams are for reference only. Package sizes are not to scale
P
24
/A12
XTAL2
XTAL1
V
SS
NC
A10/P2.3
A11/P2.4
A7/P2.0
A8/P2.1
WR/P3.6
RD/P3.7
A9/P2.2
XTAL2
XTAL1
VSS
NC
MATRA MHS
Rev.F (14 Jan. 97)
3
80C154/83C154
Pin Description
Vss
Circuit Ground Potential.
Port 2
Port 2 is an 8 bit bi-directional I/O port with internal
pullups. Port 2 pins that have 1’s written to them are
pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 2 pins that are externally
being pulled low will source current (ILL, on the data
sheet) because of the internal pullups. Port 2 emits the
high-order address byte during fetches from external
Program Memory and during accesses to external Data
Memory that use 16 bit addresses (MOVX @DPTR). In
this application, it uses strong internal pullups when
emitting 1’s. During accesses to external Data Memory
that use 8 bit addresses (MOVX @Ri), Port 2 emits the
contents of the P2 Special Function Register.
It also receives the high-order address bits and control
signals during program verification in the 83C154. Port
2 can sink or source three LS TTL inputs. It can drive
CMOS inputs without external pullups.
VCC
Supply voltage during normal, Idle, and Power Down
operation.
Port 0
Port 0 is an 8 bit open drain bi-directional I/O port. Port 0
pins that have 1’s written to them float, and in that state
can be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and data
bus during accesses to external Program and Data
Memory. In this application it uses strong internal pullups
when emitting 1’s. Port 0 also outputs the code bytes
during program verification in the 83C154. External
pullups are required during program verification. Port 0
can sink eight LS TTL inputs.
Port 3
Port 3 is an 8 bit bi-directional I/O port with internal
pullups. Port 3 pins that have 1’s written to them are
pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 3 pins that are externally
being pulled low will source current (ILL, on the data
sheet) because of the pullups. It also serves the functions
of various special features of the TEMIC 51 Family, as
listed below.
Port Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Port 1
Port 1 is an 8 bit bi-directional I/O port with internal
pullups. Port 1 pins that have 1’s written to them are
pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 1 pins that are externally
being pulled low will source current (IIL, on the data
sheet) because of the internal pullups.
Port 1 also receives the low-order address byte during
program verification. In the 83C154, Port 1 can sink or
source three LS TTL inputs. It can drive CMOS inputs
without external pullups.
2 inputs of PORT 1 are also used for timer/counter 2 :
P1.0 [T2] : External clock input for timer/counter 2. P1.1
[T2EX] : A trigger input for timer/counter 2, to be
reloaded or captured causing the timer/counter 2
interrupt.
Alternate Function
RXD (serial input port)
TXD (serial output port)
INT0 (external interrupt 0)
INT1 (external interrupt 1)
TD (Timer 0 external input)
T1 (Timer 1 external input)
WR (external Data Memory write strobe)
RD (external Data Memory read strobe)
Port 3 can sink or source three LS TTL inputs. It can drive
CMOS inputs without external pullups.
RST
A high level on this for two machine cycles while the
oscillator is running resets the device. An internal
pull-down resistor permits Power-On reset using only a
capacitor connected to VCC. As soon as the result is
applied (Vin), PORT 1, 2 and 3 are tied to 1. This
operation is achieved asynchronously even if the
oscillator is not start up.
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MATRA MHS
Rev.F (14 Jan. 97)
80C154/83C154
ALE
Address Latch Enable output for latching the low byte of
the address during accesses to external memory. ALE is
activated as though for this purpose at a constant rate of
1/6 the oscillator frequency except during an external
data memory access at which time one ALE pulse is
skipped. ALE can sink or source 8 LS TTL inputs. It can
drive CMOS inputs without an external pullup.
XTAL1
Input to the inverting amplifier that forms the oscillator.
Receives the external oscillator signal when an external
oscillator is used.
XTAL2
Output of the inverting amplifier that forms the oscillator,
and input to the internal clock generator. This pin should
be floated when an external oscillator is used.
PSEN
Program Store Enable output is the read strobe to external
Program Memory. PSEN is activated twice each machine
cycle during fetches from external Program Memory.
(However, when executing out of external Program
Memory, two activations of PSEN are skipped during
each access to external Data Memory). PSEN is not
activated during fetches from internal Program Memory.
PSEN can sink/source 8 LS TTL inputs. It can drive
CMOS inputs without an external pullup.
EA
When EA is held high, the CPU executed out of internal
Program Memory (unless the Program Counter exceeds
3FFFH). When EA is held low, the CPU executes only out
of external Program Memory. EA must not be floated.
Idle and Power Down Operation
Figure 3
shows the internal Idle and Power Down clock
configuration. As illustrated, Power Down operation
stops the oscillator. The interrupt, serial port, and timer
blocks continue to function only with external clock
(INT0, INT1, T0, T1).
Figure 3. Idle and Power Down Hardware.
Idle Mode operation allows the interrupt, serial port, and
timer blocks to continue to function with internal or
external clocks, while the clock to CPU is gated off. The
special modes are activated by software via the Special
Function Register, PCON. Its hardware address is 87H.
PCON is not bit addressable.
MATRA MHS
Rev.F (14 Jan. 97)
5
PCB Design
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