Active Delay Line, 1-Func, 5-Tap, True Output, TTL, MODULE, DIP-8
| Parameter Name | Attribute value |
| Maker | Engineered Components Co. |
| Parts packaging code | DIP |
| package instruction | QIP, |
| Contacts | 8 |
| Reach Compliance Code | unknown |
| Is Samacsys | N |
| Other features | TAP TO TAP DELAY TOL.[NS] VARIES; INTERNAL TERMINATION; MAX RISE TIME CAPTURED |
| series | F |
| JESD-30 code | R-XDIP-P8 |
| length | 12.7 mm |
| Logic integrated circuit type | ACTIVE DELAY LINE |
| Number of functions | 1 |
| Number of taps/steps | 5 |
| Number of terminals | 8 |
| Maximum operating temperature | 70 °C |
| Minimum operating temperature | |
| Output polarity | TRUE |
| Package body material | UNSPECIFIED |
| encapsulated code | QIP |
| Package shape | RECTANGULAR |
| Package form | IN-LINE |
| programmable delay line | NO |
| Certification status | Not Qualified |
| Maximum seat height | 6.35 mm |
| Maximum supply voltage (Vsup) | 5.25 V |
| Minimum supply voltage (Vsup) | 4.75 V |
| Nominal supply voltage (Vsup) | 5 V |
| surface mount | NO |
| technology | TTL |
| Temperature level | COMMERCIAL |
| Terminal form | PIN/PEG |
| Terminal pitch | 2.54 mm |
| Terminal location | DUAL |
| Total delay nominal (td) | 175 ns |
| width | 7.62 mm |
| Base Number Matches | 1 |
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