NAND Gate, CMOS, PDIP14
Parameter Name | Attribute value |
Is it Rohs certified? | incompatible |
Maker | Philips Semiconductors (NXP Semiconductors N.V.) |
package instruction | DIP, DIP14,.3 |
Reach Compliance Code | unknown |
JESD-30 code | R-PDIP-T14 |
JESD-609 code | e0 |
Load capacitance (CL) | 50 pF |
Logic integrated circuit type | NAND GATE |
MaximumI(ol) | 0.004 A |
Number of terminals | 14 |
Maximum operating temperature | 85 °C |
Minimum operating temperature | -40 °C |
Package body material | PLASTIC/EPOXY |
encapsulated code | DIP |
Encapsulate equivalent code | DIP14,.3 |
Package shape | RECTANGULAR |
Package form | IN-LINE |
power supply | 5 V |
Prop。Delay @ Nom-Sup | 35 ns |
Schmitt trigger | NO |
Nominal supply voltage (Vsup) | 5 V |
surface mount | NO |
technology | CMOS |
Temperature level | INDUSTRIAL |
Terminal surface | Tin/Lead (Sn/Pb) |
Terminal form | THROUGH-HOLE |
Terminal pitch | 2.54 mm |
Terminal location | DUAL |
Base Number Matches | 1 |