MOTOROLA
Order this document
by MCM81430/D
SEMICONDUCTOR
TECHNICAL DATA
MCM81430
1M x 8 Bit Dynamic Random
Access Module
The MCM81430 is an 8M dynamic random access memory (DRAM) module or-
ganized as 1,048,576 x 8 bits. The module is a 30-lead single-in-line memory mod-
ule (SIMM) consisting of two MCM54400AN DRAMs housed in a 20/26 J-lead small
outline package (SOJ) and mounted on a substrate along with a 0.22
µF
(min) de-
coupling capacitor mounted adjacent to each DRAM. The MCM54400AN is a
CMOS high-speed dynamic random access memory organized as 1,048,576 four-
bit words and fabricated with CMOS silicon-gate process technology.
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Three-State Data Output
Early-Write Common I/O Capability
Fast Page Mode Capability
TTL-Compatible Inputs and Outputs
RAS-Only Refresh
CAS Before RAS Refresh
Hidden Refresh
1024 Cycle Refresh: 16 ms (Max)
Consists of Two 4M DRAMs and Two 0.22
µF
(Min) Decoupling Capacitors
Unlatched Data Out at Cycle End Allows Two Dimensional Chip Selection
Fast Access Time (tRAC): MCM81430-60 = 60 ns (Max)
MCM81430-70 = 70 ns (Max)
Low Active Power Dissipation: MCM81430-60 = 1.32 W (Max)
MCM81430-70 = 1.10 W (Max)
Low Standby Power Dissipation: TTL Levels = 22 mW (Max)
CMOS Levels = 11 mW (Max)
CAS Control for Eight Common I/O Lines
Available in Edge Connector (MCM81430S) or Pin Connector (MCM81430L)
S PACKAGE
SIMM MODULE
CASE 839A-01
L PACKAGE
SIP MODULE
CASE 852A-02
TOP VIEW
VCC
CAS
DQ0
A0
A1
DQ1
A2
A3
VSS
DQ2
A4
A5
DQ3
A6
A7
DQ4
A8
A9
NC
DQ5
W
VSS
DQ6
NC
DQ7
NC
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
PIN NAMES
A0 – A9 . . . . . . . . . . . . . . Address Inputs
DQ0 – DQ7 . . . . . . . . Data Input/Output
CAS . . . . . . . . . Column Address Strobe
RAS . . . . . . . . . . . . Row Address Strobe
W . . . . . . . . . . . . . . . . . Read/Write Input
VCC . . . . . . . . . . . . . . . . . . Power (+ 5 V)
VSS . . . . . . . . . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . . . . . . . No Connection
RAS
NC
NC
VCC
©
Motorola, Inc. 1994
MOTOROLA DRAM
REV 2
3/94
MCM81430
1
FUNCTIONAL BLOCK DIAGRAM
DQ0 - DQ3
DQ
A0 - A9
RAS
CAS
W
DQ4 - DQ7
DQ
A0 - A9
RAS
CAS
W
A0 - A9
VCC
VSS
RAS
CAS
W
ABSOLUTE MAXIMUM RATINGS
(See Note)
Rating
Power Supply Voltage
Voltage Relative to VSS for Any Pin Except VCC
Data Output Current per DQ Pin
Power Dissipation
Operating Temperature Range
Storage Temperature Range
Symbol
VCC
Vin, Vout
Iout
PD
TA
Value
– 1 to + 7
– 1 to + 7
50
1.4
0 to + 70
Unit
V
V
mA
W
°C
This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is ad-
vised that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this high-impedance
circuit.
Tstg
– 55 to + 125
°C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
MCM81430
2
MOTOROLA DRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V
±
10%, TA = 0 to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
(All voltages referenced to VSS)
Parameter
Supply Voltage (Operating Voltage Range)
Symbol
VCC
VSS
Logic High Voltage, All Inputs
Logic Low Voltage, All Inputs
VIH
VIL
Min
4.5
0
2.4
– 1.0
Typ
5.0
0
—
—
Max
5.5
0
6.5
0.8
V
V
Unit
V
DC CHARACTERISTICS AND SUPPLY CURRENTS
Characteristic
VCC Power Supply Current
MCM81430-60, tRC = 110 ns
MCM81430-70, tRC = 130 ns
Symbol
ICC1
ICC2
ICC3
—
—
ICC4
—
—
ICC5
ICC6
—
—
Ilkg(I)
Ilkg(O)
VOH
VOL
– 20
– 10
2.4
—
240
200
20
10
—
0.4
µA
µA
V
V
—
140
140
2
mA
mA
1
240
200
mA
1, 2
Min
—
—
—
Max
240
200
4
Unit
mA
mA
mA
1
Notes
1
VCC Power Supply Current (Standby) (RAS = CAS = VIH)
VCC Power Supply Current During RAS Only Refresh Cycles
MCM81430-60, tRC = 110 ns
MCM81430-70, tRC = 130 ns
VCC Power Supply Current During Fast Page Mode Cycle
MCM81430-60, tPC = 45 ns
MCM81430-70, tPC = 45 ns
VCC Power Supply Current (Standby) (RAS = CAS = VCC – 0.2 V)
VCC Power Supply Current During CAS Before RAS Refresh Cycle
MCM81430-60, tRC = 110 ns
MCM81430-70, tRC = 130 ns
Input Leakage Current (0 VSS
≤
Vin
≤
VCC)
Output Leakage Current (CAS at Logic 1, VSS
≤
Vout
≤
VCC)
Output High Voltage (IOH = – 5 mA)
Output Low Voltage (IOL = 4.2 mA)
NOTES:
1. Current is a function of cycle rate and output loading; maximum current is measured at the fastest cycle rate with the output open.
2. Column address can be changed once or less while RAS = VIL and CAS = VIH.
CAPACITANCE
(f = 1.0 MHz, TA = 25°C, VCC = 5 V, Periodically Sampled Rather Than 100% Tested)
Parameter
Input Capacitance
Input/Output Capacitance
A0 – A9, W, CAS, RAS
DQ0 – DQ7
Symbol
Cin
CI/O
Max
24
17
Unit
pF
pF
NOTE: Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = I
∆t/∆V.
MOTOROLA DRAM
MCM81430
3
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V
±
10%, TA = 0 to 70°C, Unless Otherwise Noted)
READ AND WRITE CYCLES
(See Notes 1, 2, 3, and 4)
Symbol
Parameter
Random Read or Write Cycle Time
Fast Page Mode Cycle Time
Access Time from RAS
Access Time from CAS
Access Time from Column Address
Access Time from Precharge CAS
CAS to Output in Low-Z
Output Buffer and Turn-Off Delay
Transition Time (Rise and Fall)
RAS Precharge Time
RAS Pulse Width
RAS Pulse Width (Fast Page Mode)
RAS Hold Time
CAS Hold Time
CAS Precharge to RAS Hold Time
CAS Pulse Width
RAS to CAS Delay Time
RAS to Column Address Delay Time
CAS to RAS Precharge Time
CAS Precharge Time
Row Address Setup Time
Row Address Hold Time
Column Address Setup Time
Column Address Hold Time
Column Address to RAS Lead Time
Read Command Setup Time
Std
tRELREL
tCELCEL
tRELQV
tCELQV
tAVQV
tCEHQV
tCELQX
tCEHQZ
tT
tREHREL
tRELREH
tRELREH
tCELREH
tRELCEH
tCEHREH
tCELCEH
tRELCEL
tRELAV
tCEHREL
tCEHCEL
tAVREL
tRELAX
tAVCEL
tCELAX
tAVREH
tWHCEL
Alt
tRC
tPC
tRAC
tCAC
tAA
tCPA
tCLZ
tOFF
tT
tRP
tRAS
tRASP
tRSH
tCSH
tRHCP
tCAS
tRCD
tRAD
tCRP
tCP
tASR
tRAH
tASC
tCAH
tRAL
tRCS
MCM81430-60
Min
110
45
—
—
—
—
0
0
3
40
60
60
20
60
40
20
20
15
5
10
0
10
0
15
30
0
Max
—
—
60
20
30
40
—
20
50
—
10 k
200 k
—
—
—
10 k
40
30
—
—
—
—
—
—
—
—
MCM81430-70
Min
130
45
—
—
—
—
0
0
3
50
70
70
20
70
40
20
20
15
5
10
0
10
0
15
35
0
Max
—
—
70
20
35
40
—
20
50
—
10 k
200 k
—
—
—
10 k
50
35
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11
12
6, 7
6, 8
6, 9
6
6
10
Notes
5
NOTES:
(continued)
11.
VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL.
12.
An initial pause of 200
µs
is required after power-up followed by 8 RAS cycles before proper device operation is guaranteed.
13.
The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input signals must
transition between VIH and VIL (or between VIL and VIH) in a monotonic manner.
14.
AC measurements tT = 5.0 ns.
15.
The specification for tRC (min) is used only to indicate cycle time at which proper operation over the full temperature range (0°C
≤
TA
≤
70°C)
is ensured.
16.
Measured with a current load equivalent to 2 TTL (– 200
µA,
+ 4 mA) loads and 100 pF with the data output trip points set at VOH = 2.0 V
and VOL = 0.8 V.
17.
Assumes that tRCD
≤
tRCD (max).
18.
Assumes that tRCD
≥
tRCD (max).
19.
Assumes that tRAD
≥
tRAD (max).
10. tOFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels.
11. Operation within the tRCD (max) limit ensures that tRAC (max) can be met. tRCD (max) is specified as a reference point only; if tRCD is
greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC.
12. Operation within the tRAD (max) limit ensures that tRAC (max) can be met. t RAD (max) is specified as a reference point only; if tRAD is
greater than the specified tRAD (max), then access time is controlled exclusively by tAA.
MCM81430
4
MOTOROLA DRAM
READ AND WRITE CYCLES
(Continued)
Symbol
Parameter
Read Command Hold Time Referenced
to CAS
Read Command Hold Time Referenced
to RAS
Write Command Hold Time Referenced
to CAS
Write Command Pulse Width
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Data in Setup Time
Data in Hold Time
Refresh Period
Write Command Setup Time
CAS to Write Delay
RAS to Write Delay
Column Address to Write Delay Time
CAS Precharge to Write Delay Time
(Page Mode)
CAS Setup Time for CAS Before RAS
Refresh
CAS Hold Time for CAS Before RAS
Refresh
RAS Precharge to CAS Active Time
CAS Precharge Time for CAS Before
RAS Counter Time
Write Command Setup Time (Test Mode)
Write Command Hold Time (Test Mode)
Write to RAS Precharge Time (CAS
Before RAS Refresh)
Write to RAS Hold Time (CAS Before
RAS Refresh)
Std
tCEHWX
tREHWX
tCELWH
tWLWH
tWLREH
tWLCEH
tDVCEL
tCELDX
tRVRV
tWLCEL
tCELWL
tRELWL
tAVWL
tCEHWL
tRELCEL
tRELCEH
tREHCEL
tCEHCEL
tWLREL
tRELWH
tWHREL
tRELWL
Alt
tRCH
tRRH
tWCH
tWP
tRWL
tCWL
tDS
tDH
tRFSH
tWCS
tCWD
tRWD
tAWD
tCPWD
tCSR
tCHR
tRPC
tCPT
tWTS
tWTH
tWRP
tWRH
MCM81430-60
Min
0
0
10
10
20
20
0
15
—
0
50
90
60
70
5
15
0
30
10
10
10
10
Max
—
—
—
—
—
—
—
—
16
—
—
—
—
—
—
—
—
—
—
—
—
—
MCM81430-70
Min
0
0
15
15
20
20
0
15
—
0
50
100
65
70
5
15
0
40
10
10
10
10
Max
—
—
—
—
—
—
—
—
16
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
15
15
15
15
14
14
Notes
13
13
NOTES:
13. Either tRRH or tRCH must be satisfied for a read cycle.
14. These parameters are referenced to CAS leading edge in early write cycles.
15. tWCS is not a restrictive operating parameter. It is included in the data sheet as an electrical characteristic only; if tWCS
≥
t WCS (min),
the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle. If this condition
is not satisfied, the condition of the data out (at access time) is indeterminate.
MOTOROLA DRAM
MCM81430
5
RF/Wirelessly
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