GD54HCT113J datasheet, PDF - EEWORLD Datasheet

EEWORLDEEWORLD

Datasheet

Datasheet> All Categories > logic> logic> GD54HCT113J

GD54HCT113J: DescriptionJ-K Flip-Flop, 2-Func, Negative Edge Triggered, CMOS, CDIP14,; Categorylogic logic; File Size256KB，6 Pages; ManufacturerLG Semicon Co., Ltd.

Download Datasheet Parametric Compare View All

GD54HCT113J Overview

J-K Flip-Flop, 2-Func, Negative Edge Triggered, CMOS, CDIP14,

GD54HCT113J Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
package instruction	DIP, DIP14,.3
Reach Compliance Code	unknown
JESD-30 code	R-XDIP-T14
JESD-609 code	e0
Load capacitance (CL)	50 pF
Logic integrated circuit type	J-K FLIP-FLOP
Maximum Frequency@Nom-Sup	18000000 Hz
MaximumI(ol)	0.004 A
Number of functions	2
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	CERAMIC
encapsulated code	DIP
Encapsulate equivalent code	DIP14,.3
Package shape	RECTANGULAR
Package form	IN-LINE
power supply	5 V
Certification status	Not Qualified
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Trigger type	NEGATIVE EDGE
Base Number Matches	1

GD54HCT113J Related Products

	GD54HCT113J	GD54HC113J	GD74HC113	GD74HC113D	GD74HC113J	GD74HCT113D	GD74HCT113J	GD74HCT113
Description	J-K Flip-Flop, 2-Func, Negative Edge Triggered, CMOS, CDIP14,	J-K Flip-Flop, 2-Func, Negative Edge Triggered, CMOS, CDIP14,	J-K Flip-Flop, 2-Func, Negative Edge Triggered, CMOS, PDIP14,	J-K Flip-Flop, 2-Func, Negative Edge Triggered, CMOS, PDSO14,	J-K Flip-Flop, 2-Func, Negative Edge Triggered, CMOS, CDIP14,	J-K Flip-Flop, 2-Func, Negative Edge Triggered, CMOS, PDSO14,	J-K Flip-Flop, 2-Func, Negative Edge Triggered, CMOS, CDIP14,	J-K Flip-Flop, 2-Func, Negative Edge Triggered, CMOS, PDIP14,
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
package instruction	DIP, DIP14,.3	DIP, DIP14,.3	DIP, DIP14,.3	SOP, SOP14,.25	DIP, DIP14,.3	SOP, SOP14,.25	DIP, DIP14,.3	DIP, DIP14,.3
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown
JESD-30 code	R-XDIP-T14	R-XDIP-T14	R-PDIP-T14	R-PDSO-G14	R-XDIP-T14	R-PDSO-G14	R-XDIP-T14	R-PDIP-T14
JESD-609 code	e0	e0	e0	e0	e0	e0	e0	e0
Load capacitance (CL)	50 pF	50 pF	50 pF	50 pF	50 pF	50 pF	50 pF	50 pF
Logic integrated circuit type	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP
Maximum Frequency@Nom-Sup	18000000 Hz	20000000 Hz	25000000 Hz	25000000 Hz	25000000 Hz	22000000 Hz	22000000 Hz	22000000 Hz
MaximumI(ol)	0.004 A	0.004 A	0.004 A	0.004 A	0.004 A	0.004 A	0.004 A	0.004 A
Number of functions	2	2	2	2	2	2	2	2
Number of terminals	14	14	14	14	14	14	14	14
Maximum operating temperature	125 °C	125 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-55 °C	-55 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
Package body material	CERAMIC	CERAMIC	PLASTIC/EPOXY	PLASTIC/EPOXY	CERAMIC	PLASTIC/EPOXY	CERAMIC	PLASTIC/EPOXY
encapsulated code	DIP	DIP	DIP	SOP	DIP	SOP	DIP	DIP
Encapsulate equivalent code	DIP14,.3	DIP14,.3	DIP14,.3	SOP14,.25	DIP14,.3	SOP14,.25	DIP14,.3	DIP14,.3
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	IN-LINE	IN-LINE	SMALL OUTLINE	IN-LINE	SMALL OUTLINE	IN-LINE	IN-LINE
power supply	5 V	2/6 V	2/6 V	2/6 V	2/6 V	5 V	5 V	5 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
surface mount	NO	NO	NO	YES	NO	YES	NO	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	MILITARY	MILITARY	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	GULL WING	THROUGH-HOLE	GULL WING	THROUGH-HOLE	THROUGH-HOLE
Terminal pitch	2.54 mm	2.54 mm	2.54 mm	1.27 mm	2.54 mm	1.27 mm	2.54 mm	2.54 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Trigger type	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE
Maker	-	-	LG Semicon Co., Ltd.	LG Semicon Co., Ltd.	LG Semicon Co., Ltd.	LG Semicon Co., Ltd.	LG Semicon Co., Ltd.	LG Semicon Co., Ltd.

Recommended Resources

Power limit and power saving circuit

Pulse monitoring signal generation circuit composed of monostable trigger

Loudness circuit using ordinary potentiometer

Telephone additional amplifier and recording circuit

STK084G power amplifier circuit

555 economical fluorescent display filament voltage source circuit

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components