MTD3055VT4 datasheet, PDF - EEWORLD Datasheet

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MTD3055VT4: Description12A, 60V, 0.15ohm, N-CHANNEL, Si, POWER, MOSFET; CategoryDiscrete semiconductor The transistor; File Size206KB，10 Pages; ManufacturerMotorola ( NXP ); Websitehttps://www.nxp.com

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MTD3055VT4 Overview

12A, 60V, 0.15ohm, N-CHANNEL, Si, POWER, MOSFET

MTD3055VT4 Parametric

Parameter Name	Attribute value
package instruction	SMALL OUTLINE, R-PSSO-G2
Reach Compliance Code	unknown
Avalanche Energy Efficiency Rating (Eas)	72 mJ
Shell connection	DRAIN
Configuration	SINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage	60 V
Maximum drain current (Abs) (ID)	12 A
Maximum drain current (ID)	12 A
Maximum drain-source on-resistance	0.15 Ω
FET technology	METAL-OXIDE SEMICONDUCTOR
Maximum feedback capacitance (Crss)	50 pF
JESD-30 code	R-PSSO-G2
JESD-609 code	e0
Number of components	1
Number of terminals	2
Operating mode	ENHANCEMENT MODE
Maximum operating temperature	175 °C
Package body material	PLASTIC/EPOXY
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Polarity/channel type	N-CHANNEL
Maximum power consumption environment	48 W
Maximum power dissipation(Abs)	48 W
Maximum pulsed drain current (IDM)	37 A
Certification status	Not Qualified
surface mount	YES
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal location	SINGLE
transistor applications	SWITCHING
Transistor component materials	SILICON
Maximum off time (toff)	80 ns
Maximum opening time (tons)	70 ns
Base Number Matches	1

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MOTOROLA

Designer's

SEMICONDUCTOR TECHNICAL DATA

Order this document

by MTD3055V/D

TMOS V

Power Field Effect Transistor

DPAK for Surface Mount

TMOS V is a new technology designed to achieve an on–resis-

tance area product about one–half that of standard MOSFETs. This

new technology more than doubles the present cell density of our

50 and 60 volt TMOS devices. Just as with our TMOS E–FET

designs, TMOS V is designed to withstand high energy in the

avalanche and commutation modes. Designed for low voltage, high

speed switching applications in power supplies, converters and

power motor controls, these devices are particularly well suited for

bridge circuits where diode speed and commutating safe operating

areas are critical and offer additional safety margin against

unexpected voltage transients.

New Features of TMOS V

•

On–resistance Area Product about One–half that of Standard

MOSFETs with New Low Voltage, Low RDS(on) Technology

•

Faster Switching than E–FET Predecessors

Features Common to TMOS V and TMOS E–FETS

•

Avalanche Energy Specified

•

IDSS and VDS(on) Specified at Elevated Temperature

•

Static Parameters are the Same for both TMOS V and

TMOS E–FET

•

Surface Mount Package Available in 16 mm 13–inch/2500 Unit

Tape & Reel, Add T4 Suffix to Part Number

MAXIMUM RATINGS

(TC = 25°C unless otherwise noted)

Rating

Drain–Source Voltage

Drain–Gate Voltage (RGS = 1.0 MΩ)

Gate–Source Voltage – Continuous

Gate–Source Voltage

– Non–repetitive (tp

≤

10 ms)

Drain Current – Continuous @ 25°C

Drain Current

– Continuous @ 100°C

Drain Current

– Single Pulse (tp

≤

µs)

™

Data Sheet

MTD3055V

Motorola Preferred Device

N–Channel Enhancement–Mode Silicon Gate

TMOS POWER FET

12 AMPERES

60 VOLTS

RDS(on) = 0.15 OHM

CASE 369A–13, Style 2

DPAK

Symbol

VDSS

VDGR

VGS

VGSM

IDM

Value

7.3

0.32

1.75

– 55 to 175

3.13

100

71.4

260

Unit

Vdc

Vpk

Adc

Apk

Watts

W/°C

Watts

°C

°C/W

Total Power Dissipation @ 25°C

Derate above 25°C

Total Power Dissipation @ TA = 25°C, when mounted to minimum recommended pad size

Operating and Storage Temperature Range

Single Pulse Drain–to–Source Avalanche Energy – Starting TJ = 25°C

(VDD = 25 Vdc, VGS = 10 Vdc, IL = 12 Apk, L = 1.0 mH, RG = 25

Ω

)

Thermal Resistance – Junction to Case

Thermal Resistance

– Junction to Ambient

Thermal Resistance

– Junction to Ambient, when mounted to minimum recommended pad size

Maximum Temperature for Soldering Purposes, 1/8″ from case for 10 seconds

TJ, Tstg

EAS

θJC

θJA

°C

Designer’s Data for “Worst Case” Conditions

— The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit

curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.

E–FET, Designer’s and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.

Preferred

devices are Motorola recommended choices for future use and best overall value.

REV 2

Motorola TMOS

Motorola, Inc. 1996

Power MOSFET Transistor Device Data

MTD3055VT4 Related Products

	MTD3055VT4	MTD3055V
Description	12A, 60V, 0.15ohm, N-CHANNEL, Si, POWER, MOSFET	12A, 60V, 0.15ohm, N-CHANNEL, Si, POWER, MOSFET
package instruction	SMALL OUTLINE, R-PSSO-G2	SMALL OUTLINE, R-PSSO-G2
Reach Compliance Code	unknown	unknown
Avalanche Energy Efficiency Rating (Eas)	72 mJ	72 mJ
Shell connection	DRAIN	DRAIN
Configuration	SINGLE WITH BUILT-IN DIODE	SINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage	60 V	60 V
Maximum drain current (ID)	12 A	12 A
Maximum drain-source on-resistance	0.15 Ω	0.15 Ω
FET technology	METAL-OXIDE SEMICONDUCTOR	METAL-OXIDE SEMICONDUCTOR
Maximum feedback capacitance (Crss)	50 pF	50 pF
JESD-30 code	R-PSSO-G2	R-PSSO-G2
JESD-609 code	e0	e0
Number of components	1	1
Number of terminals	2	2
Operating mode	ENHANCEMENT MODE	ENHANCEMENT MODE
Maximum operating temperature	175 °C	175 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE
Polarity/channel type	N-CHANNEL	N-CHANNEL
Maximum power consumption environment	48 W	48 W
Maximum pulsed drain current (IDM)	37 A	37 A
Certification status	Not Qualified	Not Qualified
surface mount	YES	YES
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	GULL WING
Terminal location	SINGLE	SINGLE
transistor applications	SWITCHING	SWITCHING
Transistor component materials	SILICON	SILICON
Maximum off time (toff)	80 ns	80 ns
Maximum opening time (tons)	70 ns	70 ns
Base Number Matches	1	1

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