Low RMS phase jitter at 125 MHz, using 25 MHz crystal
(1.875 MHz to 20 MHz): 0.4 ps (typical)
Phase noise at 125 MHz (typical):
Offset
1 kHz
10 kHz
100 kHz
1 MHz
Noise Power
–117 dBc/Hz
–126 dBc/Hz
–131 dBc/Hz
–131 dBc/Hz
Functional Description
The CY2XP22 is a PLL (Phase Locked Loop) based high
performance clock generator that uses an external reference
crystal. It is specifically targeted at FibreChannel and Gigabit
Ethernet applications. It produces a selectable output frequency
that is 2.5 or 5 times the crystal frequency. With a 25 MHz crystal,
the user can select either a 62.5 MHz or 125 MHz output. It uses
Cypress’s low noise VCO technology to achieve less than 1 ps
typical RMS phase jitter. The CY2XP22 has a crystal oscillator
interface input and one LVPECL output pair.
Logic Block Diagram
XIN
External
Crystal
XOUT
CRYSTAL
OSCILLATOR
LOW -NOISE
PLL
OUTPUT
DIVIDER
CLK
CLK#
F _SEL
Pinouts
Figure 1. Pin Diagram – 8-Pin TSSOP
VDD
VSS
XOUT
XIN
Table 1. Pin Definitions – 8-Pin TSSOP
Pin Number
1, 8
2
3, 4
5
6,7
Pin Name
VDD
VSS
XOUT, XIN
F_SEL
CLK#, CLK
Power
Power
I/O Type
1
2
3
4
8
7
6
5
VDD
CLK
CLK#
F_SEL
Description
3.3 V or 2.5 V power supply
Ground
Parallel resonant crystal interface
Frequency Select: see Frequency Table
Differential clock output
XTAL output and input
CMOS input
LVPECL output
Cypress Semiconductor Corporation
Document #: 001-10229 Rev. *F
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 11, 2011
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CY2XP22
Frequency Table
Inputs
Crystal Frequency (MHz)
25
F_SEL
0
1
PLL Multiplier Value
5
2.5
Output Frequency (MHz)
125
62.5
Absolute Maximum Conditions
Parameter
V
DD
V
IN[1]
T
S
T
J
ESD
HBM
UL–94
Θ
JA[2]
Supply Voltage
Input Voltage, DC
Temperature, Storage
Temperature, Junction
ESD Protection, Human Body Model
Flammability Rating
Thermal Resistance, Junction to Ambient
JEDEC STD 22-A114-B
At 1/8 in.
0 m/s airflow
1 m/s airflow
2.5 m/s airflow
Relative to V
SS
Non operating
Description
Conditions
Min
–0.5
–0.5
–65
–
2000
V–0
100
91
87
°C/W
Max
4.4
V
DD
+ 0.5
150
135
–
Unit
V
V
°C
°C
V
Operating Conditions
Parameter
V
DD
T
A
T
PU
3.3 V Supply Voltage
2.5 V Supply Voltage
Ambient Temperature, Commercial
Ambient Temperature, Industrial
Power up time for all V
DD
to reach minimum specified voltage (ensure power ramps
is monotonic)
Description
Min
3.135
2.375
0
–40
0.05
Max
3.465
2.625
70
85
500
Unit
V
V
°C
°C
ms
DC Electrical Characteristics
Parameter
I
DD
Description
Operating Supply Current with
output unterminated
Test Conditions
V
DD
= 3.465 V, F
OUT
= 125 MHz,
output unterminated
V
DD
= 2.625 V, F
OUT
= 125 MHz,
output unterminated
I
DDT
Operating Supply Current with
output terminated
V
DD
= 3.465 V, F
OUT
= 125 MHz,
output terminated
V
DD
= 2.625 V, F
OUT
= 125 MHz,
output terminated
V
OH
V
OL
LVPECL Output High Voltage
LVPECL Output Low Voltage
Min
–
–
–
–
Typ
–
–
–
–
–
–
Max
125
120
150
145
V
DD
–0.75
V
DD
–1.625
Unit
mA
mA
mA
mA
V
V
V
DD
= 3.3 V or 2.5 V, R
TERM
= 50Ω to V
DD
–1.15
V
DD
– 2.0 V
V
DD
= 3.3 V or 2.5 V, R
TERM
= 50Ω to
V
DD
– 2.0 V
V
DD
–2.0
Notes
1. The voltage on any input or IO pin cannot exceed the power pin during power up.
2. Simulated using Apache Sentinel TI software. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of
copper (2/1/1/2 oz.). The internal layers are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model.
Document #: 001-10229 Rev. *F
Page 2 of 10
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CY2XP22
DC Electrical Characteristics
(continued)
Parameter
V
OD1
V
OD2
V
OCM
V
IH
V
IL
I
IH
I
IL
C
IN
[3]
Description
LVPECL Peak-to-Peak Output
Voltage Swing
LVPECL Output Voltage Swing
(V
OH
- V
OL
)
Test Conditions
V
DD
= 3.3 V or 2.5 V, R
TERM
= 50Ω to
V
DD
– 2.0 V
V
DD
= 2.5 V, R
TERM
= 50Ω to V
DD
–
1.5 V
Min
600
500
1.2
0.7*V
DD
–0.3
Typ
–
–
–
–
–
–
–
15
4.5
Max
1000
1000
–
V
DD
+ 0.3
0.3*V
DD
115
–
–
–
Unit
mV
mV
V
V
V
µA
µA
pF
pF
LVPECL Output Common Mode V
DD
= 2.5 V, R
TERM
= 50Ω to V
DD
–
Voltage (V
OH
+ V
OL
)/2
1.5 V
Input High Voltage, F_SEL
Input Low Voltage, F_SEL
Input High Current, F_SEL
Input Low Current, F_SEL
Input Capacitance, F_SEL
Pin Capacitance, XIN & XOUT
F_SEL = V
DD
F_SEL = V
SS
–
–50
–
–
C
INX[3]
AC Electrical Characteristics
[3]
Parameter
F
OUT
T
R
, T
F
T
Jitter(φ)
T
DC
T
LOCK
Description
Output Frequency
Output Rise or Fall Time
RMS Phase Jitter (Random)
Output Duty Cycle
Startup Time
20% to 80% of full output swing
125 MHz, (1.875–20 MHz)
Measured at zero crossing point
Time for CLK to reach valid
frequency measured from the time
V
DD
= V
DD
(min.)
Time for CLK to reach valid
frequency from F_SEL pin change
Conditions
Min
62.5
–
–
48
–
Typ
–
0.5
0.4
50
–
Max
125
1.0
–
52
5
Unit
MHz
ns
ps
%
ms
T
LFS
Re-lock Time
–
–
1
ms
Recommended Crystal Specifications
[4]
Parameter
Mode
F
ESR
C
0
Mode of Oscillation
Frequency
Equivalent Series Resistance
Shunt Capacitance
Description
Min
25
–
–
Max
25
50
7
Unit
MHz
Ω
pF
Fundamental
Notes
3. Not 100% tested, guaranteed by design and characterization.
4. Characterized using an 18 pF parallel resonant crystal.
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