All outputs should be uniformly loaded to achieve Zero Delay
between the input and output. Since the CLKOUT pin is the
internal feedback to the PLL, its relative loading can adjust the
input-output delay.
The output driving the CLKOUT pin will be driving a total load of
5 pF plus any additional load externally connected to this pin. For
applications requiring zero input-output delay, the total load on
each output pin (including CLKOUT) must be the same. If
input-output delay adjustments are required, the CLKOUT load
may be changed to vary the delay between the REF input and
remaining outputs.
For zero output-output skew, be sure to load all outputs equally.
For further information refer to the application note entitled
“CY2305 and CY2309 as PCI and SDRAM Buffers”.
Notes
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. Weak pull-ups on these inputs.
4. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.
Document #: 38-07760 Rev. *C
Page 4 of 17
[+] Feedback
CY23EP09
Absolute Maximum Conditions
Supply voltage to ground potential .................–0.5 V to 4.6 V
DC input voltage .....................................V
SS
– 0.5 V to 4.6 V
Storage temperature................................... –65 °C to 150 °C
Junction temperature.................................................. 150 °C
Static discharge voltage
(per MIL-STD-883, Method 3015............................. > 2000 V
Min
3.0
2.3
0
–40
–
–
–
–
–
–
–
–
1–1.5
0.8
29
41
37
41
0.01
95
70
58
48
50
Max
3.6
2.7
70
85
30
30
22
22
15
15
15
5
Unit
V
V
°C
°C
pF
pF
pF
pF
pF
pF
pF
pF
MHz
MHz
ms
°C/W
°C/W
°C/W
°C/W
Operating Conditions
Parameter
V
DD3.3
V
DD2.5
T
A
C
L[5]
3.3 V supply voltage
2.5 V supply voltage
Operating temperature (ambient temperature)—commercial
Operating temperature (ambient temperature)—industrial
Load capacitance, <100 MHz, 3.3 V
Load capacitance, <100 MHz, 2.5 V with High drive
Load capacitance, <133.3 MHz, 3.3 V
Load capacitance, <133.3 MHz, 2.5 V with High drive
Load capacitance, <133.3 MHz, 2.5 V with Standard drive
Load capacitance, >133.3 MHz, 3.3 V
Load capacitance, >133.3 MHz, 2.5 V with High drive
C
IN
BW
R
OUT
Input capacitance
[6]
Closed-loop bandwidth (typical), 3.3 V
Closed-loop bandwidth (typical), 2.5 V
Output impedance (typical), 3.3 V High drive
Output impedance (typical), 3.3 V Standard drive
Output impedance (typical), 2.5 V High drive
Output impedance (typical), 2.5 V Standard drive
t
PU
Theta Ja
[7]
Theta Jc
[7]
Power-up time for all VDD’s to reach minimum specified voltage
(power ramps must be monotonic)
Dissipation, Junction to ambient, 16-pin SOIC
Dissipation, Junction to ambient, 16-pin TSSOP
Dissipation, Junction to case, 16-pin SOIC
Dissipation, Junction to case, 16-pin TSSOP
Description
3.3 V DC Electrical Specifications
Parameter
V
DD
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
(PD mode)
I
DD
Description
Supply voltage
Input LOW voltage
Input HIGH voltage
Input leakage current
Input HIGH current
Output LOW voltage
Output HIGH voltage
Power down supply current
Supply current
0 < V
IN
< V
IL
V
IN
= V
DD
I
OL
= 8 mA (standard drive)
I
OL
= 12 mA (High drive)
I
OH
= –8 mA (standard drive)
I
OH
= –12 mA (High drive)
REF = 0 MHz (Commercial)
REF = 0 MHz (Industrial)
Unloaded outputs, 66-MHz REF
Notes
5. Applies to Test Circuit #1.
6. Applies to both REF Clock and internal feedback path on CLKOUT.
The code is as follows:
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