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QL5822-33APQN208I

Description
PCI Bus Controller, CMOS, PQFP208, 28 X 28 MM, 3.35 MM THICKNESS, 0.50 MM PITCH, LEAD FREE, PLASTIC, MS-029, QFP-208
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size1MB,76 Pages
ManufacturerQuickLogic Corporation
Websitehttps://www.quicklogic.com
Environmental Compliance  
Download Datasheet Parametric View All

QL5822-33APQN208I Overview

PCI Bus Controller, CMOS, PQFP208, 28 X 28 MM, 3.35 MM THICKNESS, 0.50 MM PITCH, LEAD FREE, PLASTIC, MS-029, QFP-208

QL5822-33APQN208I Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerQuickLogic Corporation
Parts packaging codeQFP
package instructionFQFP, QFP208,1.2SQ,20
Contacts208
Reach Compliance Codecompliant
ECCN code3A991.A.2
Address bus width32
maximum clock frequency33 MHz
Maximum data transfer rate264 MBps
External data bus width32
JESD-30 codeS-PQFP-G208
JESD-609 codee3
length28 mm
Humidity sensitivity level3
Number of terminals208
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeFQFP
Encapsulate equivalent codeQFP208,1.2SQ,20
Package shapeSQUARE
Package formFLATPACK, FINE PITCH
Peak Reflow Temperature (Celsius)245
power supply1.8,3.3 V
Certification statusNot Qualified
Maximum seat height4.1 mm
Maximum slew rate3 mA
Maximum supply voltage1.89 V
Minimum supply voltage1.71 V
Nominal supply voltage1.8 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMATTE TIN
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature40
width28 mm
uPs/uCs/peripheral integrated circuit typeBUS CONTROLLER, PCI
Base Number Matches1
QL58x2 Enhanced QuickPCI®
Family Data Sheet
• • • • • •
33/66 MHz/32-bit PCI Master/Target with Embedded Programmable
Logic, Embedded Computational Units, and Dual Port SRAM
Device Highlights
High Performance PCI Controller
• 33/66 MHz 32-bit PCI Master/Target
• Zero-wait state PCI Master provides up to
264 MBps transfer rates
• Zero-wait-state PCI Target Write/One-wait-state
PCI Target Read interface
• Supports all PCI commands, including
configuration and MWI
• Supports fully-customizable byte enable for
master channels
• Target interface supports retry, disconnect
with/without data transfer, and target abort
• Fully programmable back-end interface
• Independent PCI bus (33/66 MHz) and local bus
(up to 160 MHz) clocks
• Fully customizable PCI Configuration Space
• Configurable FIFOs with depths up to 256 words
• Reference design with driver code
(Win 95/98/2000/NT 4.0) available
• PCI v2.3 compliant
• Supports Type 0 Configuration Cycles in Target
mode
• 3.3 V PCI signaling
• 1.8 V supply voltage
• 484-ball PBGA, 280-ball LFBGA, 208-pin PQFP,
196-ball TFBGA, and 144-pin TQFP packages
• Supports Extendable PCI functionality
• Unlimited/Continuous Burst Transfers supported
Extendable PCI Functionality
• Support for Configuration Space from 0
×
40
to 0
×
3FF
• PCI v2.3 Power Management Spec. compatible
• Multi-function, expanded capabilities, and
expansion ROM capable
• PCI v2.3 Vital Product Data (VPD) configuration
support
Flexible Programmable Logic
• Up to 1,348 logic cells
• Up to 50,688 RAM bits
• Up to 262 I/O pins
• All back-end interface and glue-logic can be
implemented on chip
• Six 32-bit busses interface between the PCI
Controller and the Programmable Logic
• Up to twenty-two 2,304 bit dual-port high
performance SRAM blocks
• Up to 3,482 flip-flops available
Figure 1: QL58x2 Block Diagram
PCI Bus 33 MHz/32-Bit Address and Data
Fixed
PCI Core
Parity
Check
Parity
Gen
Mux
Target
Control
Master
Control
Mux
FIFO
32-Bit Interface
DMA
Control
Configuration
Space
User
Defined
Registers
FIFO
FIFO
Programmable
Logic
XY User I/O for Flexible Local Bus
© 2006 QuickLogic Corporation
www.quicklogic.com
1

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