HBLXT9781HC.C4 datasheet, PDF - EEWORLD Datasheet

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HBLXT9781HC.C4: DescriptionEthernet Transceiver, 8-Trnsvr, PQFP208,; CategoryWireless rf/communication Telecom circuit; File Size1MB，78 Pages; ManufacturerInphi Corporation

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HBLXT9781HC.C4 Overview

Ethernet Transceiver, 8-Trnsvr, PQFP208,

HBLXT9781HC.C4 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Inphi Corporation
package instruction	QFP, QFP208,1.2SQ,20
Reach Compliance Code	compliant
data rate	100000 Mbps
JESD-30 code	S-PQFP-G208
Number of terminals	208
Transceiver quantity	8
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Encapsulate equivalent code	QFP208,1.2SQ,20
Package shape	SQUARE
Package form	FLATPACK
power supply	3.3 V
Certification status	Not Qualified
Maximum slew rate	1100 mA
Nominal supply voltage	3.3 V
surface mount	YES
Telecom integrated circuit types	ETHERNET TRANSCEIVER
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Base Number Matches	1

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LXT9761/9781

Fast Ethernet 10/100 Multi-Port Transceiver with RMII

Datasheet

The LXT9781 is an eight-port PHY Fast Ethernet Transceiver that supports IEEE 802.3 physical

layer applications at both 10 Mbps and 100 Mbps. It provides a Reduced Media Independent

Interface (RMII) for switching and other independent port applications. The LXT9761 offers the

same features and functionality in a six-port device. This data sheet uses the singular designation

“LXT97x1” to refer to both devices.

All network ports provide a combination twisted-pair (TP) or pseudo-ECL (PECL) interface for

a 10/100BASE-TX or 100BASE-FX connection.

The LXT97x1 provides three discrete LED driver outputs for each port, as well as eight global

serial LED outputs. The device supports both half- and full-duplex operation at 10 Mbps and 100

Mbps, and requires only a single 3.3V power supply.

Applications

100BASE-T, 10/100-TX, or 100BASE-FX

Switches and multi-port NICs.

Product Features

Six or eight IEEE 802.3-compliant

10BASE-T or 100BASE-TX ports with

integrated filters

3.3V operation

Optimized for dual-high stacked R45

applications

Proprietary Optimal Signal Processing™

architecture improves SNR by 3 dB over

ideal analog filters

Robust baseline wander correction

100BASE-FX fiber-optic capability on all

ports

Supports both auto-negotiation and legacy

systems without auto-negotiation capability

JTAG boundary scan

Multiple Reduced MII (RMII) ports for

independent PHY port operation

Configurable via MDIO port or external

control pins.

Maskable interrupts

Low power consumption (390 mW per

port, typical)

208-pin PQFP (LXT9761 and LXT9781)

272-pin PBGA (LXT9781 only)

As of January 15, 2001, this document replaces the Level One document

LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII.

Order Number: 249048-001

January 2001

Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781

Contents

1.0

2.0

Pin Assignments and Signal Descriptions

....................................................10

Functional Description

...........................................................................................21

2.1

Introduction..........................................................................................................21

2.1.1 OSP™ Architecture ................................................................................21

2.1.2 Comprehensive Functionality .................................................................21

Interface Descriptions..........................................................................................22

2.2.1 10/100 Network Interface .......................................................................22

2.2.1.1 Twisted-Pair Interface ...............................................................22

2.2.1.2 Fiber Interface ...........................................................................23

2.2.2 RMII Interface.........................................................................................23

2.2.3 Configuration Management Interface .....................................................23

2.2.3.1 MDIO Management Interface ....................................................23

2.2.3.2 Hardware Control Interface .......................................................25

Operating Requirements .....................................................................................25

2.3.1 Power Requirements..............................................................................25

2.3.2 Clock Requirements ...............................................................................26

2.3.2.1 Reference Clock ........................................................................26

Initialization..........................................................................................................26

2.4.1 MDIO Control Mode ...............................................................................26

2.4.2 Hardware Control Mode .........................................................................26

2.4.3 Power-Down Mode.................................................................................27

2.4.3.1 Global (Hardware) Power Down................................................27

2.4.3.2 Port (Software) Power Down .....................................................27

2.4.4 Reset ......................................................................................................28

2.4.5 Hardware Configuration Settings ...........................................................28

Link Establishment ..............................................................................................29

2.5.1 Auto-Negotiation.....................................................................................29

2.5.1.1 Base Page Exchange................................................................29

2.5.1.2 Next Page Exchange.................................................................29

2.5.1.3 Controlling Auto-Negotiation .....................................................29

2.5.2 Parallel Detection ...................................................................................30

RMII Operation ....................................................................................................30

2.6.1 Reference Clock.....................................................................................31

2.6.2 Transmit Enable .....................................................................................31

2.6.3 Carrier Sense & Data Valid ....................................................................31

2.6.4 Receive Error .........................................................................................31

2.6.5 Loopback................................................................................................31

2.6.6 Out of Band Signalling............................................................................31

2.6.7 4B/5B Coding Operations.......................................................................32

100 Mbps Operation............................................................................................32

2.7.1 100BASE-X Network Operations ...........................................................32

2.7.2 100BASE-X Protocol Sublayer Operations ............................................33

2.7.2.1 PCS Sublayer ............................................................................33

2.7.2.2 PMA Sublayer ...........................................................................35

2.7.2.3 Twisted-Pair PMD Sublayer ......................................................36

2.7.2.4 Fiber PMD Sublayer ..................................................................37

2.2

2.3

2.4

2.5

2.6

2.7

Datasheet

LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII

2.8

2.9

2.10

10 Mbps Operation.............................................................................................. 37

2.8.1 Preamble Handling................................................................................. 37

2.8.2 Dribble Bits............................................................................................. 38

2.8.3 Link Test................................................................................................. 38

2.8.3.1 Link Failure................................................................................ 38

2.8.4 Jabber .................................................................................................... 38

Monitoring Operations......................................................................................... 38

2.9.1 Monitoring Auto-Negotiation................................................................... 38

2.9.2 Serial LED Functions ............................................................................. 38

2.9.3 Per-Port LED Driver Functions............................................................... 40

2.9.3.1 LED Pulse Stretching ................................................................ 40

2.9.4 Using the Quick Status Register ............................................................ 41

2.9.5 Out-of-Band Signalling ........................................................................... 42

Boundary Scan (JTAG1149.1) Functions ........................................................... 42

2.10.1 Boundary Scan Interface........................................................................ 42

2.10.2 State Machine ........................................................................................ 42

2.10.3 Instruction Register ................................................................................ 43

2.10.4 Boundary Scan Register ........................................................................ 43

Design Recommendations .................................................................................. 44

3.1.1 General Design Guidelines .................................................................... 44

3.1.2 Power Supply Filtering ........................................................................... 44

3.1.3 Power and Ground Plane Layout Considerations .................................. 45

3.1.3.1 Chassis Ground......................................................................... 45

3.1.4 RMII Terminations .................................................................................. 45

3.1.5 The RBIAS Pin ....................................................................................... 45

3.1.6 The Twisted-Pair Interface ..................................................................... 46

3.1.6.1 Magnetics Information ............................................................... 46

3.1.7 The Fiber Interface................................................................................. 46

Typical Application Circuits ................................................................................. 46

3.0

Application Information

......................................................................................... 44

3.1

3.2

4.0

5.0

6.0

Test Specifications

.................................................................................................. 52

................................................................................................ 62

Package Specifications

......................................................................................... 77

Datasheet

Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781

Figures

LXT9781 Block Diagram ....................................................................................... 9

LXT9781 PQFP Pin Assignments .......................................................................10

LXT9781 PBGA Pin Assignments ......................................................................11

LXT9761 PQFP Pin Assignments .......................................................................12

LXT97x1 Interfaces ............................................................................................22

Port Address Scheme .........................................................................................24

Management Interface Read Frame Structure ...................................................24

Management Interface Write Frame Structure ...................................................24

Interrupt Logic .....................................................................................................25

Initialization Sequence .......................................................................................27

Hardware Control Settings .................................................................................28

Auto-Negotiation Operation ................................................................................30

Loopback Paths ..................................................................................................31

RMII Data Flow ...................................................................................................32

100BASE-X Frame Format ................................................................................33

Protocol Sublayers .............................................................................................34

Serial LED Streams.............................................................................................39

LED Pulse Stretching ..........................................................................................41

Quick Status Register..........................................................................................41

RMII Programmable Out of Band Signalling .......................................................42

Power and Ground Supply Connections ............................................................47

Typical Twisted-Pair Interface ............................................................................48

Typical Fiber Interface ........................................................................................49

Typical RMII Interface ........................................................................................50

Typical Serial LED Interface................................................................................51

100BASE-TX Receive Timing ...........................................................................55

100BASE-TX Transmit Timing ..........................................................................55

100BASE-FX Receive Timing ...........................................................................56

100BASE-FX Transmit Timing ..........................................................................57

10BASE-T Receive Timing ................................................................................57

10BASE-T Transmit Timing ...............................................................................58

Auto-Negotiation and Fast Link Pulse Timing ...................................................59

Fast Link Pulse Timing .......................................................................................59

MDIO Write Timing (MDIO Sourced by MAC) ....................................................60

MDIO Read Timing (MDIO Sourced by PHY) ....................................................60

Power-Up Timing ................................................................................................61

RESET And Power-Down Recovery Timing ......................................................61

PHY Identifier Bit Mapping .................................................................................67

LXT97x1 PQFP Specification .............................................................................77

LXT9781 PBGA Specification .............................................................................78

Tables

LXT97x1 RMII Signal Descriptions......................................................................13

LXT97x1 Signal Detect/TP Select Signal Descriptions .......................................15

LXT97x1 Network Interface Signal Descriptions .................................................16

LXT97x1 JTAG Test Signal Descriptions ............................................................16

LXT97x1 Miscellaneous Signal Descriptions ......................................................17

Datasheet

HBLXT9781HC.C4 Related Products

	HBLXT9781HC.C4	HBLXT9761HC.C4	FWLXT9781BC.C4	HBLXT9781HC.C5
Description	Ethernet Transceiver, 8-Trnsvr, PQFP208,	Ethernet Transceiver, 6-Trnsvr, PQFP208,	Ethernet Transceiver, 8-Trnsvr, PBGA272,	Ethernet Transceiver, 8-Trnsvr, PQFP208,
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible
Maker	Inphi Corporation	Inphi Corporation	Inphi Corporation	Inphi Corporation
package instruction	QFP, QFP208,1.2SQ,20	QFP, QFP208,1.2SQ,20	BGA, BGA272,20X20,50	QFP, QFP208,1.2SQ,20
Reach Compliance Code	compliant	compliant	compliant	compliant
data rate	100000 Mbps	100000 Mbps	100000 Mbps	100000 Mbps
JESD-30 code	S-PQFP-G208	S-PQFP-G208	S-PBGA-B272	S-PQFP-G208
Number of terminals	208	208	272	208
Transceiver quantity	8	6	8	8
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QFP	QFP	BGA	QFP
Encapsulate equivalent code	QFP208,1.2SQ,20	QFP208,1.2SQ,20	BGA272,20X20,50	QFP208,1.2SQ,20
Package shape	SQUARE	SQUARE	SQUARE	SQUARE
Package form	FLATPACK	FLATPACK	GRID ARRAY	FLATPACK
power supply	3.3 V	3.3 V	3.3 V	3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum slew rate	1100 mA	828 mA	1100 mA	1100 mA
Nominal supply voltage	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES
Telecom integrated circuit types	ETHERNET TRANSCEIVER	ETHERNET TRANSCEIVER	ETHERNET TRANSCEIVER	ETHERNET TRANSCEIVER
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	GULL WING	GULL WING	BALL	GULL WING
Terminal pitch	0.5 mm	0.5 mm	1.27 mm	0.5 mm
Terminal location	QUAD	QUAD	BOTTOM	QUAD
Base Number Matches	1	1	1	1

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