Data Sheet - Preliminary Information
OCTOBER, 1999
Revision 1.0
LXT9761 / 9781
General Description
The LXT9781 is an eight-port PHY Fast Ethernet
Transceiver that supports IEEE 802.3 physical layer
applications at both 10 Mbps and 100 Mbps. It provides a
Reduced Media Independent Interface (RMII) for
switching and other independent port applications. The
LXT9761 offers the same features and functionality in a
six-port device. This data sheet uses the singular
designation “LXT97x1” to refer to both devices.
All network ports provide a combination twisted-pair (TP)
or pseudo-ECL (PECL) interface for a 10/100BASE-TX or
100BASE-FX connection.
The LXT97x1 provides three discrete LED driver outputs
for each port, as well as eight global serial LED outputs.
The device supports both half- and full-duplex operation at
10 Mbps and 100 Mbps, and requires only a single 3.3V
power supply.
Fast Ethernet 10/100 Multi-Port Transceiver with RMII
Features
• Six or eight IEEE 802.3-compliant 10BASE-T or
100BASE-TX ports with integrated filters
• 3.3V operation
• Optimized for dual-high stacked R45 applications
• Proprietary Optimal Signal Processing™ architecture
improves SNR by 3 dB over ideal analog filters
• Robust baseline wander correction
100BASE-FX fiber-optic capability on all ports
• Supports both auto-negotiation and legacy systems
without auto-negotiation capability
• JTAG boundary scan
• Multiple Reduced MII (RMII) ports for independent
PHY port operation
• Configurable via MDIO port or external control pins.
• Maskable interrupts
• Low power consumption (378 mW per port, typical)
• 208-pin PQFP (LXT9761 and LXT9781)
• 272-pin PBGA (LXT9781 only)
Applications
• 100BASE-T, 10/100-TX, or 100BASE-FX Switches
and multi-port NICs.
LXT9781 Block Diagram
REFCLK
QSTAT
QCLK
ADD<4:0>
MDIO
MDC
MDINT
Management /
Mode Select
Logic
Global Functions
Clock
Generator
Pwr Supply /
PwrDown
8
Register Set
TXENn
TX PCS
RMII
T X D
n_0
T X D
n_1
Parallel/Serial
Converter
Manchester
10
Encoder
Scrambler
100
& Encoder
Auto
Negotiation
TP
Driver
+
-
+
-
TP / Fiber
Out
VCC
GND
PWRDWN
RESET
LEDS<7:0>
LEDLATCH
LEDCLK
O S P
TM
Pulse
Shaper
TPFOPn
TPFONn
Mgmt Counters
Register Set
CIM
ECL
Driver
S D
n
/TX
n
O S P
TM
Clock
Generator
Media
Select
Adaptive EQ
with BaseLine
Wander
Cancellation
100TX
+
-
+
100FX
RMII
RX PCS
R X D
n
_0
R X D
n
_1
CRS_DVn
RXERn
Serial to
Parallel
Carrier Sense Converter
Data Valid
Error Detect
10
Manchester
Decoder
OSP
TM
TP / Fiber
In
TPFIP
n
TPFIN
n
Decoder &
100
Descrambler
Slicer
10BT
-
+
PORT 0
Per-Port Functions
-
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
PORT 6
PORT 7
Refer to www.level1.com for most current information.
)
LXT9761 / 9781 Fast Ethernet 10/100 Multi-Port Transceiver with RMII
TABLE OF CONTENTS
Pin Assignments and Signal Descriptions .......... 4
Functional Description ........................................ 17
Introduction ....................................................... 17
OSP™ Architecture .......................................... 17
Comprehensive Functionality............................ 17
Interface Descriptions....................................... 17
10/100 Network Interface.................................. 17
Twisted-Pair Interface .................................. 18
Fiber Interface.............................................. 18
RMII Interface ................................................... 18
Configuration Management Interface................ 18
MDIO Management Interface ...................... 18
MII Addressing........................................ 19
MII Interrupts .......................................... 20
Hardware Control Interface.......................... 20
Operating Requirements .................................. 21
Power Requirements ........................................ 21
Clock Requirements.......................................... 21
Reference Clock .......................................... 21
Initialization........................................................ 21
MDIO Control Mode .......................................... 21
Hardware Control Mode.................................... 21
Power-Down Mode ........................................... 22
Reset ................................................................ 22
Hardware Configuration Settings ...................... 23
Link Establishment ........................................... 24
Auto-Negotiation ............................................... 24
Base Page Exchange .................................. 24
Next Page Exchange ................................... 24
Controlling Auto-Negotiation........................ 24
Parallel Detection.............................................. 24
RMII Operation ...................................................25
Reference Clock................................................25
Transmit Enable ................................................25
Carrier Sense & Data Valid ...............................25
Receive Error ....................................................25
Loopback...........................................................25
Out of Band Signalling ......................................25
4B/5B Coding Operation ...................................25
100 Mbps Operation ..........................................26
100BASE-X Network Operation ........................26
100BASE-X Protocol Sublayer Operations .......27
PCS Sublayer ..............................................27
4B/5B Coding Table .....................................28
PMA Sublayer ..............................................29
Twisted-Pair PMD Sublayer .........................29
Fiber PMD Sublayer.....................................30
10 Mbps Operation ............................................30
Preamble Handling............................................30
Dribble Bits........................................................30
Link Test ............................................................30
Link Failure ..................................................30
Jabber ...............................................................30
Monitoring Functions ........................................31
Monitoring Auto-Negotiation..............................31
Serial LED Functions ........................................31
Per-Port LED Driver Functions..........................32
Using the Quick Status Register .......................33
Out of Band Signalling ......................................34
Boundary Scan (JTAG) Functions ...................35
Boundary Scan Interface...................................35
State Machine ...................................................35
Instruction Register ...........................................35
Boundary Scan Register ...................................35
2
LXT9761 / 9781 Table of Contents
TABLE OF CONTENTS
Application Information .......................................36
Design Recommendations................................36
General Design Guidelines ...............................36
Power Supply Filtering ......................................36
Power and Ground Plane Layout ......................37
Chassis Ground ...........................................37
MII Terminations ................................................37
The RBIAS pin...................................................37
Twisted-Pair Interface........................................37
Magnetics Information..................................37
Fiber Interface ...................................................37
Typical Application Circuits ..............................39
Power and Ground Supply Connections ...........39
Typical Twisted-Pair Interface ...........................40
Typical Fiber Interface .......................................41
Test Specifications ...............................................44
Absolute Maximum Ratings...............................44
Operating Conditions.........................................44
Digital I/O Characteristics..................................45
Digital I/O Characteristics - RMII Pins ...............45
Required Clock Characteristics .........................45
100BASE-TX Transceiver Characteristics.........46
100BASE-FX Transceiver Characteristics.........46
10BASE-T Transceiver Characteristics .............47
100BASE-TX Receive Timing ..........................48
100BASE-TX Transmit Timing .........................49
100BASE-FX Receive Timing ...........................50
100BASE-FX Transmit Timing ..........................51
10BASE-T Receive Timing................................52
10BASE-T Transmit Timing ...............................53
Auto-Negotiation and Fast Link Pulse Timing ...54
MDIO and RMII Timing......................................55
Power-Down Timing ..........................................56
Register Definitions ............................................. 57
Register Bit Map ............................................... 58
Control Register (Address 0) ............................ 60
Status Register (Address 1).............................. 61
PHY Identification Register 1 (Address 2) ........ 62
PHY Identification Register 2 (Address 3) ........ 62
Auto-Negotiation Advertisement Register
(Address 4) ....................................................... 63
Auto-Negotiation Link Partner Ability Register
(Address 5) ....................................................... 64
Auto-Negotiation Expansion Register
(Address 6) ....................................................... 65
Auto-Negotiation Next Page Transmit Register
(Address 7) ....................................................... 66
Auto-Negotiation Link Partner Next Page
Receive Register (Address 8)........................... 66
Port Configuration Register (Address 16 .......... 67
Quick Status Register (Address 17) ................. 68
Interrupt Enable Register (Address 18) ............ 69
Interrupt Status Register (Address 19) ............. 70
LED Configuration Register (Address 20) ........ 71
Out of Band Signalling Register (Address 25) .. 73
Transmit Control Register #1 (Address 28) ...... 74
Transmit Control Register #2 (Address 30) ...... 74
Package Specification ......................................... 75
Revision History................................................... 81
3
LXT9761 / 9781 Fast Ethernet 10/100 Multi-Port Transceiver with RMII
PIN ASSIGNMENTS AND SIGNAL DESCRIPTIONS
Figure 1: LXT9781 PQFP Pin Assignments
208....... VCCIO
207....... QCLK
206....... QSTAT
205....... LED/CFG0_3
204....... LED/CFG0_2
203....... LED/CFG0_1
202....... LED/CFG1_3
201....... LED/CFG1_2
200....... LED/CFG1_1
199....... LED/CFG2_3
198....... LED/CFG2_2
197....... LED/CFG2_1
196....... LED/CFG3_3
195....... LED/CFG3_2
194....... LED/CFG3_1
193....... VCCIO
192....... GNDD
191....... LED/CFG4_3
190....... LED/CFG4_2
189....... LED/CFG4_1
188....... LED/CFG5_3
187....... LED/CFG5_2
186....... LED/CFG5_1
185....... LED/CFG6_3
184....... LED/CFG6_2
183....... LED/CFG6_1
182....... LED/CFG7_3
181....... LED/CFG7_2
180....... LED/CFG7_1
179....... VCCD
178....... GNDD
177....... LEDS0
176....... LEDS1
175....... LEDS2
174....... LEDS3
173....... LEDS4
172....... LEDS5
171....... LEDS6
170....... LEDS7
169....... LEDLATCH
168....... LEDCLK
167....... TRST
166....... TCK
165....... TMS
164....... TDO
163....... TDI
162....... SIGDET4
161....... SIGDET5
160....... SIGDET6
159....... SIGDET7
158....... GNDA
157....... TPFIP7
GNDD ..... 1
RXD7_1 ..... 2
RXD7_0 ..... 3
CRS_DV7 ..... 4
RXER7 ..... 5
TXEN7 ..... 6
TXD7_0 ..... 7
TXD7_1 ..... 8
RXD6_1 ..... 9
RXD6_0 ..... 10
CRS_DV6 ..... 11
RXER6 ..... 12
TXEN6 ..... 13
TXD6_0 ..... 14
VCCIO ..... 15
GNDD ..... 16
TXD6_1 ..... 17
RXD5_1 ..... 18
RXD5_0 ..... 19
CRS_DV5 ..... 20
RXER5 ..... 21
TXEN5 ..... 22
TXD5_0 ..... 23
TXD5_1 ..... 24
RXD4_1 ..... 25
RXD4_0 ..... 26
CRS_DV4 ..... 27
RXER4 ..... 28
TXEN4 ..... 29
TXD4_0 ..... 30
VCCIO ..... 31
GNDD ..... 32
TXD4_1 ..... 33
RXD3_1 ..... 34
RXD3_0 ..... 35
CRS_DV3 ..... 36
RXER3 ..... 37
TXEN3 ..... 38
TXD3_0 ..... 39
TXD3_1 ..... 40
RXD2_1 ..... 41
RXD2_0 ..... 42
CRS_DV2 ..... 43
RXER2 ..... 44
TXEN2 ..... 45
TXD2_0 ..... 46
TXD2_1 ..... 47
GNDD ..... 48
GNDD ..... 49
GNDD ..... 50
GNDD ..... 51
VCCIO ..... 52
(Date Code)
(Part#)
XXXX XXXX
LXT9781HC
XXXXXX
(Lot#)
156 ....... TPFIN7
155 ....... VCCR
154 ....... TPFOP7
153 ....... TPFON7
152 ....... GNDA
151 ....... TPFON6
150 ....... TPFOP6
149 ....... VCCT
148 ....... VCCR
147 ....... TPFIN6
146 ....... TPFIP6
145 ....... GNDA
144 ....... GNDA
143 ....... TPFIP5
142 ....... TPFIN5
141 ....... VCCR
140 ....... TPFOP5
139 ....... TPFON5
138 ....... GNDA
137 ....... TPFON4
136 ....... TPFOP4
135 ....... VCCT
134 ....... VCCR
133 ....... TPFIN4
132 ....... TPFIP4
131 ....... GNDA
130 ....... GNDA
129 ....... TPFIP3
128 ....... TPFIN3
127 ....... VCCR
126 ....... VCCT
125 ....... TPFOP3
124 ....... TPFON3
123 ....... GNDA
122 ....... TPFON2
121 ....... TPFOP2
120 ....... VCCR
119 ....... TPFIN2
118 ....... TPFIP2
117 ....... GNDA
116 ....... GNDA
115 ....... TPFIP1
114 ....... TPFIN1
113 ....... VCCR
112 ....... VCCT
111 ....... TPFOP1
110 ....... TPFON1
109 ....... GNDA
108 ....... TPFON0
107 ....... TPFOP0
106 ....... VCCR
105 ....... TPFIN0
1. Ports 6 and 7 are available only on the LXT9781. These ports are not bonded out on the LXT9761.
GNDD......53
RXD1_1......54
RXD1_0......55
CRS_DV1......56
RXER1......57
TXEN1......58
TXD1_0......59
TXD1_1......60
RXD0_1......61
RXD0_0......62
CRS_DV0......63
RXER0......64
TXEN0......65
TXD0_0......66
VCCIO......67
GNDD......68
TXD0_1......69
MDC......70
MDIO......71
GNDD......72
GNDD......73
GNDD......74
GNDD......75
TxSLEW_0......76
TxSLEW_1......77
GNDS......78
PAUSE......79
VCCD......80
GNDD......81
PWRDWN......82
RESET......83
MDINT......84
MDDIS......85
GNDD......86
GNDD......87
VCCD......88
GNDD......89
GNDD......90
GNDD......91
REFCLK......92
ADD_0......93
ADD_1......94
ADD_2......95
ADD_3......96
ADD_4......97
SIGDET3......98
SIGDET2......99
SIGDET1......100
SIGDET0......101
RBIAS......102
GNDA......103
TPFIP0......104
4
LXT9761 / 9781 Pin Assignments and Signal Descriptions
Figure 2: LXT9781 PBGA Pin Assignments
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
NC
2
NC
3
QCLK
4
5
6
7
8
9
10
11
12
13
14
15
16
TRST
17
SD6/
TP6
SD5/
TP5
SD7/
TP7
18
VCCT
19
TP
FIN7
TP
FON7
TP
FOP6
TP
FIP6
20
TP
FIP7
TP
FOP7
TP
FON6
TP
FIN6
LED/
LED/
LED/
LED/
LED/
LED/
LED/
GNDD CFG1_2 CFG2_2 CFG3_1 CFG4_2 CFG5_2 CFG6_1 CFG7_3 VCCD
LED/
G N D D C F G 5 _ 3 LED/
VCCD
CFG6_2
LEDS_4 LEDS_3 LEDS_7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
NC
LED/
LED/
G N D D C R S _ D V 7 Q S T A T C F G 0 _ 1 LED/
CFG2_3 CFG3_3
RXD7
_0
VCCD
LEDS_1 LEDS_5
LED
CLK
TMS
VCCT
RXD7
_1
GNDD
LED/
LED/
LED/
LED/
LED/
GNDD LEDS_2 LEDS_6
V C C I O C F G 0 _ 3 LED/ C F G 2 _ 1 C F G 4 _ 1 C F G 6 _ 3 LED/
CFG1_3
CFG7_2 CFG7_1
TXD7
_1
LED/
LED/
LED/
LED/
LED/
GNDD
CFG0_2 CFG1_1 CFG3_2 CFG4_3 CFG5_1
LEDS
_0
LED
LATCH
TDO
SD4/
TP4
GNDA
RXER7
TXEN7
TXD7
_0
RXD6
_0
VCCIO
TDI
TCK
GNDA
VCCR
GNDA
RXD6
_1
GNDD
GNDD
VCCR
GNDA
VCCT
VCCT
CRS_DV6 RXER6 TXEN6
TXD6
_0
VCCIO
TXD6
_1
GNDD
GNDD
TOP VIEW
LXT9781BC
GNDD
GNDD
GNDD
GNDD
GNDA
GNDA
TP
FIN5
TP
FON5
TP
FOP4
TP
FIN4
TP
FIP5
TP
FOP5
TP
FON4
TP
FIP4
GNDA
GNDA
RXD5
_1
GNDD
RXD5
_0
TXD5
_0
RXD4
_0
TXD4
_0
CRS_
DV5
TXD5
_1
CRS_
DV4
VCCR
GNDA
RXER5 TXEN5
VCCR
GNDA
GNDD
RXD4
_1
GNDD
GNDD
GNDD
GNDD
GNDA
GNDA
VCCT
VCCT
RXER4
TXEN4
TXD4_1
GNDD
GNDD
GNDD
GNDD
GNDA
GNDA
VCCT
VCCT
VCCIO
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
VCCR
GNDA
TP
FIN3
TP
FON3
TP
FOP2
TP
FIP2
TP
FIP3
TP
FOP3
TP
FON2
TP
FIN2
RXD3
_1
RXD3
_0
CRS_
DV3
TXD3
_0
CRS_
DV2
TXD2
_1
RXER3
VCCR
GNDA
TXEN3
GNDD
TXD3
_1
GNDA
GNDA
RXD2
_1
RXD2
_0
TXD2
_0
RXER2
GNDA
GNDA
TXEN2
GNDD
VCCR
GNDA
VCCT
VCCT
NC
NC
NC
NC
GNDD
RXD0
_1
CRS_
DV0
RXD0
_0
TXD0
_0
GNDD
NC TxSLEW_1 GNDD
MDINT
SD1/
TP1
SD2/
TP2
SD3/
TP3
GNDA
VCCR
GNDA
TP
FIN1
TP
FON1
TP
FOP0
TP
FIP0
TP
FIP1
TP
FOP1
TP
FON0
TP
FIN0
VCCIO
RXD1
_1
RXER1
TXD1
_1
TXD1
_0
GNDD
MDC
NC
GNDS
GNDD
RESET
ADD_2
ADD_1 ADD_3
SD0/
TP0
ADD_4
RBIAS
GNDA
NC
GNDD
TXEN1
GNDD
RXER0 TXD0_1
MDIO
NC
PAUSE
GNDD PWRDWN GNDD
GNDD
ADD_0
GNDA
VCCT
NC
RXD1
_0
CRS_
DV1
NC
TXEN0
VCCIO
NC
TxSLEW_0 VCCD
VCCD
VCCD
MDDIS G N D D
GNDD REFCLK GNDD
GNDD
VCCT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1. Ports 6 and 7 are available only on the LXT9781.
5