Document Revision History
Version History
Rev 0
Rev 1.0
Rev 2.0
Pre-release, Alpha customers only
Initial Public Release
Added output voltage maximum value and note to clarify in
Table 10-1;
also removed overall life
expectancy note, since life expectancy is dependent on customer usage and must be
determined by reliability engineering. Clarified value and unit measure for Maximum allowed P
D
in
Table 10-3.
Corrected note about average value for Flash Data Retention in
Table 10-4.
Added new RoHS-compliant orderable part numbers in
Table 13-1.
Corrected Data Flash on page 5
Deleted RSTO from Pin Group 2 (listed after
Table 10-1).
Deleted formula for Max Ambient
Operating Temperature (Automotive) and Max Ambient Operating Temperature (Industrial) in
Table 10-4.
Added RoHS-compliance and “pb-free” language to back cover.
Added information/corrected state during reset in
Table 2-2.
Clarified external reference crystal
frequency for PLL in
Table 10-14
by increasing maximum value to 8.4MHz.
Replaced “Tri-stated” with an explanation in State During Reset column in
Table 2-2.
• Added the following note to the description of the TMS signal in
Table 2-2:
Note:
Always tie the TMS pin to V
DD
through a 2.2K resistor.
• Added the following note to the description of the TRST signal in
Table 2-2:
Note:
For normal operation, connect TRST directly to V
SS
. If the design is to be used in a debugging
environment, TRST may be tied to V
SS
through a 1K resistor.
Rev. 8
• Remove pullup comment from PWM pins in
Table 2-2.
• Add
Figure 10-1
showing current voltage characteristics.
• In
Table 10-23,
correct interpretation of Calibration Factors to be viewed as worst case
factors.
• Add to
Table 10-23
the DC drift of ADC over temperature.
Description of Change
Rev 3.0
Rev 4.0
Rev 5.0
Rev 6.0
Rev. 7
Please see http://www.freescale.com for the most current data sheet revision.
56F8365 Technical Data, Rev. 8
2
Freescale Semiconductor
Preliminary
Table of Contents
Part 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1
1.2
1.3
1.4
1.5
1.6
56F8365/56F8165 Features . . . . . . . . . . . .5
Device Description. . . . . . . . . . . . . . . . . . . .8
Award-Winning Development Environment10
Architecture Block Diagram . . . . . . . . . . . .10
Product Documentation . . . . . . . . . . . . . . .13
Data Sheet Conventions . . . . . . . . . . . . . .14
Part 8 General Purpose Input/Output (GPIO)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
8.1
8.2
8.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . 133
Memory Maps . . . . . . . . . . . . . . . . . . . . . 133
Configuration. . . . . . . . . . . . . . . . . . . . . . 133
Part 9 Joint Test Action Group (JTAG) . . 138
9.1
JTAG Information . . . . . . . . . . . . . . . . . . 138
Part 2 Signal/Connection Descriptions . . . . 14
2.1
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . .14
Signal Pins. . . . . . . . . . . . . . . . . . . . . . . . .18
Part 10 Specifications . . . . . . . . . . . . . . . . 138
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
10.10
10.11
10.12
10.13
10.14
10.15
10.16
10.17
General Characteristics. . . . . . . . . . . . . . 138
DC Electrical Characteristics. . . . . . . . . . 143
AC Electrical Characteristics . . . . . . . . . . 148
Flash Memory Characteristics. . . . . . . . . 148
External Clock Operation Timing . . . . . . 149
Phase Locked Loop Timing. . . . . . . . . . . 149
Crystal Oscillator Timing . . . . . . . . . . . . . 150
Reset, Stop, Wait, Mode Select, and
Interrupt Timing . . . . . . . . . . . . . . . 150
Serial Peripheral Interface (SPI) Timing . 153
Quad Timer Timing . . . . . . . . . . . . . . . . . 157
Quadrature Decoder Timing . . . . . . . . . . 157
Serial Communication Interface (SCI)
Timing. . . . . . . . . . . . . . . . . . . . . . . 158
Controller Area Network (CAN) Timing . . 159
JTAG Timing . . . . . . . . . . . . . . . . . . . . . . 159
Analog-to-Digital Converter (ADC)
Parameters . . . . . . . . . . . . . . . . . . . 161
Equivalent Circuit for ADC Inputs . . . . . . 163
Power Consumption . . . . . . . . . . . . . . . . 164
Part 3 On-Chip Clock Synthesis (OCCS) . . . 36
3.1
3.2
3.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . .36
External Clock Operation. . . . . . . . . . . . . .36
Registers . . . . . . . . . . . . . . . . . . . . . . . . . .38
Part 4 Memory Map . . . . . . . . . . . . . . . . . . . . 38
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
Introduction . . . . . . . . . . . . . . . . . . . . . . . .38
Program Map . . . . . . . . . . . . . . . . . . . . . . .39
Interrupt Vector Table . . . . . . . . . . . . . . . .41
Data Map . . . . . . . . . . . . . . . . . . . . . . . . . .44
Flash Memory Map . . . . . . . . . . . . . . . . . .45
EOnCE Memory Map. . . . . . . . . . . . . . . . .46
Peripheral Memory Mapped Registers . . .47
Factory Programmed Memory . . . . . . . . . .79
Part 5 Interrupt Controller (ITCN) . . . . . . . . . 79
5.1
5.2
5.3
5.4
5.5
5.6
5.7
Introduction . . . . . . . . . . . . . . . . . . . . . . . .79
Features. . . . . . . . . . . . . . . . . . . . . . . . . . .79
Functional Description . . . . . . . . . . . . . . . .80
Block Diagram . . . . . . . . . . . . . . . . . . . . . .81
Operating Modes . . . . . . . . . . . . . . . . . . . .81
Register Descriptions. . . . . . . . . . . . . . . . .82
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Part 11 Packaging . . . . . . . . . . . . . . . . . . . 166
11.1
11.2
56F8365 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . . . 166
56F8165 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . . . 169
Part 6 System Integration Module (SIM) . . 110
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
Introduction . . . . . . . . . . . . . . . . . . . . . . .110
Features. . . . . . . . . . . . . . . . . . . . . . . . . .110
Operating Modes . . . . . . . . . . . . . . . . . . .111
Operating Mode Register. . . . . . . . . . . . .111
Register Descriptions. . . . . . . . . . . . . . . .112
Clock Generation Overview . . . . . . . . . . .127
Power-Down Modes Overview . . . . . . . .127
Stop and Wait Mode Disable Function . .128
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . .128
12.1
12.2
12.3
Part 12 Design Considerations . . . . . . . . . 174
Thermal Design Considerations . . . . . . . 174
Electrical Design Considerations . . . . . . 175
Power Distribution and I/O Ring
Implementation . . . . . . . . . . . . . . . . 176
Part 13 Ordering Information . . . . . . . . . . 178
Part 7 Security Features . . . . . . . . . . . . . . . 129
7.1
7.2
Operation with Security Enabled . . . . . . .129
Flash Access Blocking Mechanisms . . . .129
56F8365 Technical Data, Rev. 8
Freescale Semiconductor
Preliminary
3
TI Technology Forum
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