White Electronic Designs
W3EG72128S-AD4
-BD4
PRELIMINARY*
1GB – 2x64Mx72 DDR SDRAM UNBUFFERED ECC w/PLL
FEATURES
Double-data-rate architecture
DDR200, DDR266 and DDR333
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect
Dual Rank
Power supply: 2.5V ± 0.20V
JEDEC standard 200 pin SO-DIMM package
• Package height options:
AD4: 35.5 mm (1.38") and
BD4: 31.75 mm (1.25")
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
* This product is under development, is not qualified or characterized and is subject to
change without notice.
DESCRIPTION
The W3EG72128S is a 2x64Mx72 Double Data Rate
SDRAM memory module based on 512Mb DDR SDRAM
components. This module consists of eighteen 64Mx8 bit
DDR SDRAMs in 66 pin TSOP packages mounted on a
200 pin FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
OPERATING FREQUENCIES
DDR333 @CL=2.5
Clock Speed
CL-t
RCD
-t
RP
166MHz
2.5-3-3
DDR266 @CL=2
133MHz
2-2-2
DDR266 @CL=2.5
133MHz
2.5-3-3
DDR200 @CL=2
100MHz
2-2-2
August 2005
Rev. 3
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
PIN CONFIGURATION
PIN#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
SYMBOL PIN#
V
REF
51
V
REF
52
53
V
SS
V
SS
54
DQ0
55
DQ4
56
DQ1
57
DQ5
58
V
CC
59
V
CC
60
DQS0
61
DQM0
62
DQ2
63
DQ6
64
65
V
SS
V
SS
66
DQ3
67
DQ7
68
DQ8
69
DQ12
70
V
CC
71
72
V
CC
DQ9
73
DQ13
74
DQS1
75
DQM1
76
V
SS
77
78
V
SS
DQ10
79
DQ14
80
DQ11
81
DQ15
82
V
CC
83
V
CC
84
CK0
85
V
CC
86
CK0#
87
V
SS
88
V
SS
89
90
V
SS
DQ16
91
DQ20
92
DQ17
93
DQ21
94
V
CC
95
V
CC
96
DQS2
97
DQM2
98
DQ18
99
DQ22
100
SYMBOL PIN#
V
SS
101
V
SS
102
DQ19
103
DQ23
104
DQ24
105
DQ28
106
V
CC
107
V
CC
108
DQ25
109
DQ29
110
DQS3
111
DQM3
112
V
SS
113
V
SS
114
DQ26
115
DQ30
116
DQ27
117
DQ31
118
V
CC
119
V
CC
120
CB0
121
CB4
122
CB1
123
CB5
124
V
SS
125
V
SS
126
DQS8
127
DQM8
128
NC
129
CB6
130
V
CC
131
V
CC
132
CB3
133
CB7
134
NC
135
NC
136
V
SS
137
V
SS
138
NC
139
V
SS
140
NC
141
V
CC
142
V
CC
143
V
CC
144
CKE1
145
CKE0
146
NC
147
NC
148
A12
149
A11
150
SYMBOL PIN#
A9
151
A8
152
V
SS
153
V
SS
154
A7
155
A6
156
A5
157
A4
158
A3
159
A2
160
A1
161
A0
162
V
CC
163
V
CC
164
A10/AP
165
BA1
166
BA0
167
RAS#
168
WE#
169
CAS#
170
CS0#
171
CS1#
172
NC
173
NC
174
V
SS
175
V
SS
176
DQ32
177
DQ36
178
DQ33
179
DQ37
180
V
CC
181
V
CC
182
DQS4
183
DQM4
184
DQ34
185
DQ38
186
V
SS
187
V
SS
188
DQ35
189
DQ39
190
DQ40
191
DQ44
192
V
CC
193
V
CC
194
DQ41
195
DQ45
196
DQS5
197
DQM5
198
V
SS
199
V
SS
200
SYMBOL
DQ42
DQ46
DQ43
DQ47
V
CC
V
CC
V
CC
NC
V
SS
NC
V
SS
V
SS
DQ48
DQ52
DQ49
DQ53
V
CC
V
CC
DQS6
DQM6
DQ50
DQ54
V
SS
V
SS
DQ51
DQ55
DQ56
DQ60
V
CC
V
CC
DQ57
DQ61
DQS7
DQM7
V
SS
V
SS
DQ58
DQ62
DQ59
DQ63
V
CC
V
CC
SDA
SA0
SCL
SA1
V
CCSPD
SA2
V
CCID
NC
W3EG72128S-AD4
-BD4
PRELIMINARY
PIN NAMES
A0-A12
BA0-BA1
DQ0-DQ63
DQS0-DQS8
CK0
CK0#
CKE0, CKE1
CS0#, CS1#
RAS#
CAS#
WE#
DQM0-DQM8
V
CC
V
SS
V
REF
V
CCSPD
SDA
SCL
SA0-SA2
V
CCID
NC
Address input (Multiplexed)
Bank Select Address
Data Input/Output
Data Strobe Input/Output
Clock Input
Clock Input
Clock Enable input
Chip Select Input
Row Address Strobe
Column Address Strobe
Write Enable
Data-In Mask
Power Supply (2.5V)
Ground
Power Supply for Reference
Serial EEPROM Power Supply
(2.3V to 3.6V)
Serial data I/O
Serial clock
Address in EEPROM
V
CC
Indentification Flag
No Connect
August 2005
Rev. 3
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
FUNCTIONAL BLOCK DIAGRAM
W3EG72128S-AD4
-BD4
PRELIMINARY
CS1#
CS0#
DQS0
DQM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DQM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DQM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS8
DQM8
CS#
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQS
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
CS#
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7
DQM7
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQS
CS#
CS#
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS6
DQM6
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQS
CS#
CS#
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
DQM5
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQS
CS#
DQS4
DQM4
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQS
CS#
CS#
V
CC
120Ω
CK0
CK0A
CLK0/CLK0#
CLK1/CLK1#
PLL
CK0#
CK0A#
CLK2/CLK2#
CLK3/CLK3#
RAS#
CAS#
BA0-BA1
WE#
A0-A12
CKE0
CKE1
RAS: DDR SDRAMs
FEEDBACK
CAS: DDR SDRAMs
BA0-BA1: DDR SDRAMs
WE: DDR SDRAMs
A0-A12: DDR SDRAMs
SCL
SERIAL PD
SDA
A0
SA0
A1
SA1
A2
SA2
CKE0: DDR SDRAMs
CKE1: DDR SDRAMs
V
CC
GND
DDR SDRAM
DDR SDRAM
Note: All datalines are terminated through a 22 ohms series resistor.
August 2005
Rev. 3
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
SS
Voltage on V
CC
supply relative to V
SS
Storage Temperature
Power Dissipation
Short Circuit Current
Note:
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
W3EG72128S-AD4
-BD4
PRELIMINARY
Symbol
V
IN
, V
OUT
V
CC
, V
CCQ
T
STG
P
D
I
OS
Value
-0.5 to 3.6
-1.0 to 3.6
-55 to +150
9
50
Units
V
V
°C
W
mA
DC CHARACTERISTICS
0°C
≤
T
A
≤
70°C, V
CC
= 2.5V ± 0.2V
Symbol
V
CC
V
CCQ
V
REF
V
TT
V
IH
V
IL
V
OH
V
OL
Parameter
Supply Voltage
Supply Voltage
Reference Voltage
Termination Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Min
2.3
2.3
V
CCQ/2
- 50mV
V
REF
- 0.04
V
REF
+ 0.15
-0.3
V
TT
+ 0.76
—
Max
2.7
2.7
V
CCQ/2
+ 50mV
V
REF
+ 0.04
V
CCQ
+ 0.3
V
REF
- 0.15
—
V
TT
- 0.76
Unit
V
V
V
V
V
V
V
V
CAPACITANCE
T
A
= 25°C, f = 1MHz, V
CC
= 3.3V, V
REF
=1.4V
±
200mV
Parameter
Input Capacitance (A0-A12)
Input Capacitance (RAS#, CAS#, WE#)
Input Capacitance (CKE0)
Input Capacitance (CK0,CK0#)
Input Capacitance (CS0#)
Input Capacitance (DQM0-DQM8)
Input Capacitance (BA0-BA1)
Data input/output capacitance (DQ0-DQ63)(DQS)
Symbol
C
IN1
C
IN2
C
IN3
C
IN4
C
IN5
C
IN6
C
IN7
C
OUT
Max
56
56
29
5.5
29
13
56
13
Unit
pF
pF
pF
pF
pF
pF
pF
pF
August 2005
Rev. 3
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
W3EG72128S-AD4
-BD4
PRELIMINARY
Recommended operating conditions, 0°C
≤
T
A
≤
70°C, V
CCQ
= 2.5V ± 0.2V, V
CC
= 2.5V ± 0.2V
Parameter
Symbol Conditions
One device bank; Active - Precharge;
t
RC
=t
RC
(MIN); t
CK
=t
CK
(MIN); DQ,DM
and DQS inputs changing once per
clock cycle; Address and control
inputs changing once every two
cycles.
One device bank; Active-Read-
Precharge; Burst = 2; t
RC
=t
RC
(MIN)
;t
CK
=t
CK
(MIN); Iout = 0mA; Address
and control inputs changing once per
clock cycle.
All device banks idle; Power- down
mode; t
CK
=t
CK
(MIN); CKE=(low)
CS# = High; All device banks idle;
t
CK
=t
CK
(MIN); CKE = high; Address
and other control inputs changing
once per clock cycle. Vin = Vref for
DQ, DQS and DM.
One device bank active; Power-down
mode; t
CK
(MIN); CKE=(low)
CS# = High; CKE = High; One
device bank; Active-Precharge;
t
RC
=t
RAS
(MAX); t
CK
=t
CK
(MIN); DQ,
DM and DQS inputs changing twice
per clock cycle; Address and other
control inputs changing once per
clock cycle.
Burst = 2; Reads; Continous burst;
One device bank active;Address
and control inputs changing once
per clock cycle; t
CK
=t
CK
(MIN); Iout
= 0mA.
Burst = 2; Writes; Continous burst;
One device bank active; Address
and control inputs changing once per
clock cycle; t
CK
=t
CK
(MIN); DQ,DM
and DQS inputs changing twice per
clock cycle.
t
RC
=t
RC
(MIN)
CKE
≤
0.2V
Four bank interleaving Reads (BL=4)
with auto precharge with t
RC
=t
RC
(MIN); t
CK
=t
CK
(MIN); Address and
control inputs change only during
Active Read or Write commands.
DDR333@CL=2.5 DDR266@CL=2 DDR266@CL=2.5 DDR200@CL=2
Max
Max
Max
Max
Units
IDD SPECIFICATIONS AND TEST CONDITIONS
Operating Current
I
DD0
2620
2620
2620
2620
mA
Operating Current
I
DD1
2890
2890
2890
2890
mA
Precharge Power-
Down Standby Current
I
DD2P
90
90
90
90
mA
Idle Standby Current
I
DD2F
1085
1085
1085
1085
mA
Active Power-Down
Standby Current
I
DD3P
630
630
630
630
mA
Active Standby Current
I
DD3N
1175
1175
1175
1175
mA
Operating Current
I
DD4R
2935
2935
2935
2935
mA
Operating Current
I
DD4W
3025
2845
2845
2845
mA
Auto Refresh Current
Self Refresh Current
I
DD5
I
DD6
4060
360
4060
365
4060
365
4060
365
mA
mA
Operating Current
I
DD7A
5095
5050
5050
5050
mA
August 2005
Rev. 3
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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