QS5991-2JRC datasheet, PDF - EEWORLD Datasheet

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QS5991-2JRC: DescriptionPLL Based Clock Driver, QS5 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PQCC32, PLASTIC, LCC-32; Categorylogic logic; File Size122KB，8 Pages; ManufacturerIDT (Integrated Device Technology)

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QS5991-2JRC Overview

PLL Based Clock Driver, QS5 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PQCC32, PLASTIC, LCC-32

QS5991-2JRC Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFJ
package instruction	QCCJ, LDCC32,.5X.6
Contacts	32
Reach Compliance Code	not_compliant
series	QS5
Input adjustment	STANDARD
JESD-30 code	R-PQCC-J32
JESD-609 code	e0
length	13.97 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
MaximumI(ol)	0.046 A
Humidity sensitivity level	1
Number of functions	1
Number of inverted outputs
Number of terminals	32
Actual output times	8
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC32,.5X.6
Package shape	RECTANGULAR
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Prop。Delay @ Nom-Sup	0.25 ns
propagation delay (tpd)	0.25 ns
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.5 ns
Maximum seat height	3.55 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	11.43 mm
minfmax	100 MHz
Base Number Matches	1

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QS5991

PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

PROGRAMMABLE SKEW

PLL CLOCK DRIVER

TURBOCLOCK™

FEATURES:

•

4 pairs of programmable skew outputs

Low skew: 200ps same pair, 250ps all outputs

Selectable positive or negative edge synchronization:

Excellent for DSP applications

Synchronous output enable

Output frequency: 6.25MHz to 100MHz

2x, 4x, 1/2, and 1/4 outputs

5V with TTL outputs

3 skew grades:

QS5991 -2: t

SKEW0

<250ps

QS5991 -5: t

SKEW0

<500ps

QS5991 -7: t

SKEW0

<750ps

3-level inputs for skew and PLL range control

PLL bypass for DC testing

External feedback, internal loop filter

46mA I

high drive outputs

Low Jitter: <200ps peak-to-peak

Outputs drive 50Ω terminated lines

Pin compatible with Cypress CY7B991

Available in PLCC Package

QS5991

DESCRIPTION:

The QS5991 is a high fanout PLL based clock driver intended for

high performance computing and data-communications applications. A

key feature of the programmable skew is the ability of outputs to lead or

lag the REF input signal. The QS5991 has eight programmable skew

outputs in four banks of 2. Skew is controlled by 3-level input signals

that may be hard-wired to appropriate HIGH-MID-LOW levels.

The QS5991 maintains Cypress CY7B991 compatibility while pro-

viding two additional features: Synchronous Output Enable (GND/sOE),

and Positive/Negative Edge Synchronization (V

CCQ

/PE). When the GND/

sOE

pin is held low, all the outputs are synchronously enabled (CY7B991

compatibility). However, if GND/sOE is held high, all the outputs except

3Q0 and 3Q1 are synchronously disabled.

Furthermore, when the V

CCQ

/PE is held high, all the outputs are

synchronized with the positive edge of the REF clock input (CY7B991

compatibility). When V

CCQ

/PE is held low, all the outputs are synchro-

nized with the negative edge of REF.

•

FUNCTIONAL BLOCK DIAGRAM

G ND/sOE

Skew

Select

1F1:0

CCQ

/PE

Skew

Select

REF

PLL

Skew

Select

3F1:0

2F1:0

Skew

Select

4F1:0

COMMERCIAL/INDUSTRIAL TEMPERATURE RANGES

2000

Integrated Device Technology, Inc.

MARCH 2000

DSC-5809/-

QS5991-2JRC Related Products

	QS5991-2JRC	QS5991-5JRI
Description	PLL Based Clock Driver, QS5 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PQCC32, PLASTIC, LCC-32	PLL Based Clock Driver, QS5 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PQCC32, PLASTIC, LCC-32
Is it lead-free?	Contains lead	Contains lead
Is it Rohs certified?	incompatible	incompatible
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	QFJ	QFJ
package instruction	QCCJ, LDCC32,.5X.6	QCCJ, LDCC32,.5X.6
Contacts	32	32
Reach Compliance Code	not_compliant	not_compliant
series	QS5	QS5
Input adjustment	STANDARD	STANDARD
JESD-30 code	R-PQCC-J32	R-PQCC-J32
JESD-609 code	e0	e0
length	13.97 mm	13.97 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER
MaximumI(ol)	0.046 A	0.046 A
Humidity sensitivity level	1	1
Number of functions	1	1
Number of terminals	32	32
Actual output times	8	8
Maximum operating temperature	70 °C	85 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QCCJ	QCCJ
Encapsulate equivalent code	LDCC32,.5X.6	LDCC32,.5X.6
Package shape	RECTANGULAR	RECTANGULAR
Package form	CHIP CARRIER	CHIP CARRIER
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	225
power supply	5 V	5 V
Prop。Delay @ Nom-Sup	0.25 ns	0.5 ns
propagation delay (tpd)	0.25 ns	0.5 ns
Certification status	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	0.5 ns	0.7 ns
Maximum seat height	3.55 mm	3.55 mm
Maximum supply voltage (Vsup)	5.25 V	5.5 V
Minimum supply voltage (Vsup)	4.75 V	4.5 V
Nominal supply voltage (Vsup)	5 V	5 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	COMMERCIAL	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)
Terminal form	J BEND	J BEND
Terminal pitch	1.27 mm	1.27 mm
Terminal location	QUAD	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED	30
width	11.43 mm	11.43 mm
minfmax	100 MHz	100 MHz

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