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W232
Ten Output Zero Delay Buffer
Features
■
■
■
■
Key Specifications
■
■
■
■
■
■
Well-Suited to both 100 and 133 MHz Designs
10 or 11 LVCMOS/LVTTL Outputs
3.3V Power Supply
Available in 24-Pin TSSOP Package
Operating Voltage: 3.3V ± 10%
Operating Range: 25 MHz < f
OUT
< 140 MHz
Cycle-to-Cycle Jitter less than 150 ps
Output to Output Skew less than100 ps
Phase Error Jitter less than 125 ps
Static Phase Error: less than 150 ps
Logic Block Diagram
FBIN
CLK
PLL
FBOUT
Q0
Q1
Q2
OE0:4
Q3
OE
Q4
Q5
OE5:8
Q6
Q7
Q8
Q9
Configuration of these blocks dependent upon specific option being used.
Pinouts
Figure 1. 24-Pin TSSOP - W232-09
AGND
VDD
Q0
Q1
Q2
GND
GND
Q3
Q4
VDD
OE0:4
FBOUT
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLK
AVDD
VDD
Q8
Q7
GND
GND
Q6
Q5
VDD
OE5:8
FBIN
Figure 2. 24-Pin TSSOP - W232-10
AGND
VDD
Q0
Q1
Q2
GND
GND
Q3
Q4
VDD
OE
FBOUT
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLK
AVDD
VDD
Q9
Q8
GND
GND
Q7
Q6
Q5
VDD
FBIN
W232-10
Cypress Semiconductor Corporation
Document #: 38-07167 Rev. *E
W232-09
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 27, 2009
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W232
Pin Definitions
Pin Name
CLK
FBIN
Pin No.
(-09)
24
13
Pin No.
(-10)
24
13
Pin Type
I
I
Pin Description
Reference Input: Output signals Q0:9 are synchronized to this signal.
Feedback Input: This input must be fed by one of the outputs (typically FBOUT)
to ensure proper functionality. If the trace between FBIN and FBOUT is equal
in length to the traces between the outputs and the signal destinations, then the
signals received at the destinations are synchronized to the CLK signal input.
Outputs: The frequency and phase of the signals provided by these pins are
equal to the reference signal if properly laid out.
Feedback Output: Typically this is connected directly to the FBIN input with a
trace equal in length to the traces between outputs Q0:9 and the destination
points of these output signals.
Analog Power Connection: Connect to 3.3V. Use ferrite beads to help reduce
noise for optimal jitter performance.
Analog Ground Connection: Connect to common system ground plane.
Power Connections: Connect to 3.3V. Use ferrite beads to help reduce noise
for optimal jitter performance.
Ground Connections: Connect to common system ground plane.
Output Enable Input: Tie to V
DD
(HIGH, 1) for normal operation. When brought
to GND (LOW, 0) outputs Q0:4 are disabled to a LOW state.
Output Enable Input: Tie to V
DD
(HIGH, 1) for normal operation. When brought
to GND (LOW, 0) outputs Q0:9 are disabled to a LOW state.
Output Enable Input: Tie to V
DD
(HIGH, 1) for normal operation. When brought
to GND (LOW, 0) outputs Q5:8 are disabled to a LOW state.
Q0:8
FBOUT
3, 4, 5, 8, 9, 3, 4, 5, 8, 9, 15,
16, 17, 20, 21 16, 17, 20, 21
12
12
O
O
AVDD
AGND
VDD
GND
OE0:4
OE
OE5:8
23
1
2, 10, 15, 22
6, 7, 18, 19
11
–
14
23
1
2, 10, 14 22
6, 7, 18, 19
–
11
–
P
G
P
G
I
I
I
Overview
The W232 is a PLL-based clock driver designed for use in systems requiring a large number of synchronous timing signals. The clock
driver has output frequencies of up to 140 MHz and output-to-output skews of less than 100 ps. The W232 provides minimum
cycle-to-cycle and long-term jitter, which is of significant importance to meet the tight input-to-input skew budget in DIMM applications.
The W232 was specifically designed to accept SSFTG signals currently being used in motherboard designs to reduce EMI. Zero delay
buffers which are not designed to pass this feature through may cause skewing failures.
Output enable pins allow shutdown of output when they are not being used. This reduces EMI and power consumption.
Document #: 38-07167 Rev. *E
Page 2 of 6
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W232
Figure 3. Schematic
1
AGND
VDD
Q0
Q1
Q2
GND
GND
Q3
Q4
VDD
OE
FBOUT
GND
AVDD
VDD
Q9
Q8
GND
GND
Q7
Q6
Q5
VDD
FBIN
24
23
22
21
20
19
18
17
16
15
14
13
VDD
0.1
μF
2
3
4
5
6
7
8
9
0.1
μF
FB
3.3V
0.1
μF
10
μF
10
μF
VDD
FB
W232-10
VDD
0.1
μF
10
11
12
0.1
μF
VDD
Spread Aware
Many systems being designed now use a technology called
Spread Spectrum Frequency Timing Generation (SSFTG).
Cypress has been one of the pioneers of SSFTG development,
and designed this product so as not to filter off the Spread
Spectrum (SS) feature of the Reference input, assuming it exists.
When a zero delay buffer is not designed to pass the SS feature
through, the result is a significant amount of tracking skew which
may cause problems in systems requiring synchronization.
For more details on SS timing technology, see the Cypress appli-
cation note titled, “EMI
Suppression Techniques with Spread
Spectrum Frequency Timing Generator (SSFTG) ICs” - AN1278.
Inserting Other Devices in Feedback Path
Another nice feature available due to the external feedback is the
ability to synchronize signals up to the signal coming from some
other device. This implementation can be applied to any device
(ASIC, multiple output clock buffer/driver, and so on) which is put
into the feedback path.
As shown in
Figure 4,
if the traces between the ASIC/buffer and
the destination of the clock signal(s) (A) are equal in length to the
trace between the buffer and the FBIN pin, the signals at the
destination(s) device are driven HIGH at the same time the
Reference clock provided to the ZDB goes HIGH. Synchronizing
the other outputs of the ZDB to the outputs form the ASIC/Buffer
is, however, more complex as any propagation delay in the
ASIC/Buffer must be accounted for.
Figure 4. 6 Output Buffer in the Feedback Path
Reference
Signal
How to Implement Zero Delay
Typically, Zero Delay Buffers (ZDBs) are used because a
designer wants to provide multiple copies of a clock signal in
phase with each other. The whole concept behind ZDBs is that
the signals at the destination chips are all going HIGH at the
same time as the input to the ZDB. To achieve this, layout must
compensate for trace length between the ZDB and the target
devices. The method of compensation is as follows.
External feedback is the trait that allows this compensation.
Since the PLL on the ZDB causes the feedback signal to be in
phase with the reference signal, when laying out the board,
match the trace lengths between the output being used for
feedback and the FBIN input to the PLL.
If it is desirable to either add a little delay, or slightly precede the
input signal, this may also be affected by either making the trace
to the FBIN pin a little shorter or a little longer than the traces to
the devices being clocked.
Zero
Delay
Buffer
Feedback
Input
ASIC/
Buffer
A
Document #: 38-07167 Rev. *E
Page 3 of 6
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W232
Absolute Maximum Ratings
[1]
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only.
Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not
implied. Maximum conditions for extended periods may affect reliability.
.
Parameter
V
DD
, V
IN
T
STG
T
A
T
B
P
D
Description
Voltage on any Pin with Respect to GND
Storage Temperature
Operating Temperature
Ambient Temperature under Bias
Power Dissipation
Rating
–0.5 to +7.0
–65 to +150
0 to +70
–55 to +125
0.5
Unit
V
°C
°C
°C
W
DC Electrical Characteristics
:
T
A
= 0°C to 70°C, V
DD
= 3.3V ±10%
Parameter
I
DD
V
IL
V
IH
V
OL
V
OH
I
IL
I
IH
Description
Supply Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Current
Input High Current
I
OL
= 12 mA
I
OH
= –12 mA
V
IN
= 0V
V
IN
= V
DD
2.1
50
50
2.0
0.8
Test Condition
Unloaded, 100 MHz
Min
Typ
Max
200
0.8
Unit
mA
V
V
V
V
μA
μA
AC Electrical Characteristics:
T
A
= 0°C to +70°C, V
DD
= 3.3V ±10%
Parameter
f
OUT
t
R
t
F
tI
CLKR
tI
CLKF
t
PEJ
t
SK
t
D
t
LOCK
t
JC
Description
Output Frequency
Output Rise Time
Output Fall Time
Input Clock Rise Time
[2]
Input Clock Fall Time
[2]
CLK to FBIN Skew
Variation
[3, 4]
Duty Cycle
PLL Lock Time
Jitter, Cycle-to-Cycle
[5]
Measured at V
DD
/2
–350
–100
43
0
0
50
Test Condition
30-pF load
[5]
Min
25
Typ
Max
140
2.1
2.5
4.5
4.5
350
100
58
1.0
150
Unit
MHz
ns
ns
ns
ns
ps
ps
%
ms
ps
0.8V to 2.0V, 30-pF load
2.0V to 0.8V, 30-pF load
Output to Output Skew All outputs loaded equally
30-pF load
Power supply stable
Notes
1. Multiple Supplies: The voltage on any input or IO pin cannot exceed the power pin during power up. Power supply sequencing is NOT required.
2. Longer input rise and fall time degrades skew and jitter performance.
3. Skew is measured at V
DD
/2 on rising edges.
4. Duty cycle is measured at V
DD
/2.
5. Production tests are run at 133 MHz.
6. For frequencies below 40 MHz, Cycle-to-Cycle Jitter degrades to 175 ps.
Document #: 38-07167 Rev. *E
Page 4 of 6
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