V54C3256(16/80)4VK
256Mbit SDRAM, 3.3 VOLT
16M X 16, 32M X 8
6
System Frequency (f
CK
)
Clock Cycle Time (t
CK3
)
Clock Access Time (t
AC3
) CAS Latency = 3
Clock Access Time (t
AC2
) CAS Latency = 2
166 MHz
6 ns
5.4 ns
5.4 ns
7
143 MHz
7 ns
5.4 ns
6 ns
Features
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Description
The V54C3256(16/80)4VK is a four bank Syn-
chronous DRAM organized as 4 banks x 4Mbit x 16,
or 4 banks x 8Mbit x 8. The V54C3256(16/80)4VJ
achieves high speed data transfer rates up to 166
MHz by employing a chip architecture that prefetch-
es multiple bits and then synchronizes the output
data to a system clock.
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
166 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
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4 banks x 4Mbit x 16 organization
4 banks x 8Mbit x 8 organization
High speed data transfer rates up to 166 MHz
Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
Single Pulsed RAS Interface
Data Mask for Read/Write Control
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 3
Programmable Wrap Sequence: Sequential or
Interleave
Programmable Burst Length:
1, 2, 4, 8 and full page for Sequential Type
1, 2, 4, 8 for Interleave Type
Multiple Burst Read with Single Write Operation
Automatic and Controlled Precharge Command
Random Column Address every CLK (1-N Rule)
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 8192 cycles/64 ms
Available in 54 Pin TSOP II and 54 Ball FBGA
LVTTL Interface
Single +3.3 V ±0.3 V Power Supply
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
-25°C to 85°C
-40°C to 85°C
Package Outline
54 Pin TSOP II
54 Ball FBGA
•
•
•
6
•
•
•
Access Time (ns)
7
•
•
•
Power
Std.
•
•
•
Temperature
Mark
Blank
M
I
V54C3256(16/80)4VK Rev. 1 March 2019
1
ProMOS TECHNOLOGIES
Capacitance*
V
CC
= 3.3 V ± 0.3 V, f = 1 Mhz
Symbol Parameter
C
I1
C
I2
C
IO
C
CLK
Input Capacitance (A0 to A12)
Input Capacitance
RAS, CAS, WE, CS, CLK, CKE, DQM
Output Capacitance (I/O)
Input Capacitance (CLK)
V54C3256(16/80)4VK
Absolute Maximum Ratings*
Operating temperature range ..........0 to 70 °C for normal
-25 to 85 °C (-M)
-40 to 85 °C ( -I )
Storage temperature range .........................-55 to 150 °C
Input/output voltage ........................... -0.3 to (V
CC
+0.3) V
Power supply voltage ................................... -0.3 to 4.6 V
Power dissipation ...................................................... 1 W
Data out current (short circuit) ............................... 50 mA
*Note:
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage of the device.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Max. Unit
5
5
6.5
4
pF
pF
pF
pF
*Note:Capacitance is sampled and not 100% tested.
Block Diagram
x16 Configuration
Column Addresses
A0 - A8, AP, BA0, BA1
Row Addresses
A0 - A12, BA0, BA1
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
Row decoder
Memory array
Column decoder
Sense amplifier & I(O) bus
Row decoder
Memory array
Bank 1
Row decoder
Memory array
Bank 2
Row decoder
Memory array
Bank 3
Bank 0
8192 x 512
x 16 bit
Column decoder
Sense amplifier & I(O) bus
8192 x 512
x16 bit
Column decoder
Sense amplifier & I(O) bus
8192 x 512
x 16 bit
Column decoder
Sense amplifier & I(O) bus
8192 x 512
x 16 bit
Input buffer
Output buffer
Control logic & timing generator
I/O
1
-I/O
16
LDQM
WE
UDQM
CKE
RAS
CLK
CAS
CS
V54C3256(16/80)4VK Rev1 March 2019
5
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