XD-14597D5-572Q datasheet, PDF

XD-14597D5-572Q: DescriptionSynchro or Resolver to Digital Converter, Hybrid, DDIP-36; CategoryAnalog mixed-signal IC converter; File Size417KB，14 Pages; ManufacturerData Device Corporation

Download Datasheet Parametric View All

XD-14597D5-572Q Overview

Synchro or Resolver to Digital Converter, Hybrid, DDIP-36

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	DIP
package instruction	DDIP-36
Contacts	36
Reach Compliance Code	compliant
ECCN code	EAR99
Other features	BUILT-IN-TEST, PROGRAMMABLE RESOLUTION
Maximum analog input voltage	1.15 V
Maximum angular accuracy	5.2 arc min
Converter type	SYNCHRO OR RESOLVER TO DIGITAL CONVERTER
JESD-30 code	R-XDIP-P36
JESD-609 code	e0
Number of digits	16
Number of functions	1
Number of terminals	36
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	UNSPECIFIED
encapsulated code	QIP
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	5.69 mm
Signal/output frequency	60 Hz
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	NO
technology	HYBRID
Temperature level	INDUSTRIAL
Terminal surface	TIN LEAD
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15.24 mm
Base Number Matches	1

Goodbye 2018, hello 2019: Say goodbye to 2018 and welcome 2019! I hope everyone will not dwell on the past, start a new journey, and ignite new hope! EEWorld celebrates the New Year with everyone....; okhxyyo Talking

STM32 related altium library files (F0, F1, F2, F3, F4, etc.): This content is originally created by EEWORLD forum user chenzhufly . If you want to reprint or use it for commercial purposes, you must obtain the author's consent and indicate the source...; chenzhufly stm32/stm8

"Me and Intel SoC FPGA" + ARM hardcore development that is difficult to understand: [i=s]This post was last edited by a media student on 2019-5-12 14:46[/i] [font=微软雅黑][size=4] [/size][/font] [align=center][md]#[size=3][color=#0000ff]“Me and Intel SoC FPGA” + Incomprehensible ARM har...; 传媒学子 FPGA/CPLD

Practical capacitor voltage step-down circuit: The conventional method of converting AC mains power into low-voltage DC is to use a transformer to step down the voltage and then rectify and filter it. When limited by factors such as size and cost,...; 木犯001号 Power technology

Today's award-winning live broadcast: 5G and edge computing development and technology applications: 5G is a key technology that will change the entire technology world. Through the three major application scenarios, 5G has spawned a large number of different applications with significantly different...; EEWORLD社区 RF/Wirelessly

[AT-START-F403A Evaluation] 4. QR code scanning test: [i=s] This post was last edited by lmyyz on 2020-10-12 16:19[/i]Let’s first take a look at the demo program provided by the original manufacturer, the main function: int main(void) {static u8 bartype=...; lmyyz Domestic Chip Exchange

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components