EDI88512LPA20F36I datasheet, PDF

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EDI88512LPA20F36I: DescriptionStandard SRAM, 512KX8, 20ns, CMOS, CDFP36, CERAMIC, DFP-36; Categorystorage storage; ManufacturerMercury Systems Inc

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EDI88512LPA20F36I Overview

Standard SRAM, 512KX8, 20ns, CMOS, CDFP36, CERAMIC, DFP-36

EDI88512LPA20F36I Parametric

Parameter Name	Attribute value
package instruction	DFP,
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Maximum access time	20 ns
Other features	TTL COMPATIBLE INPUTS/OUTPUTS
JESD-30 code	R-CDFP-F36
length	23.368 mm
memory density	4194304 bit
Memory IC Type	STANDARD SRAM
memory width	8
Number of functions	1
Number of terminals	36
word count	524288 words
character code	512000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	512KX8
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DFP
Package shape	RECTANGULAR
Package form	FLATPACK
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	3.175 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	FLAT
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	12.954 mm
Base Number Matches	1

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EDI88512CA

512Kx8 Monolithic SRAM, SMD 5962-95600

FEATURES



Access Times of 15, 17, 20, 25, 35, 45, 55ns



Data Retention Function (LPA version)



TTL Compatible Inputs and Outputs



Fully Static, No Clocks



Organized as 512Kx8



Commercial, Industrial and Military Temperature Ranges



32 lead JEDEC Approved Evolutionary Pinout

• Ceramic Sidebrazed 600 mil DIP (Package 9)

• Ceramic Sidebrazed 400 mil DIP (Package 326)

• Ceramic 32 pin Flatpack (Package 344)

• Ceramic Thin Flatpack (Package 321)

• Ceramic SOJ (Package 140)



36 lead JEDEC Approved Revolutionary Pinout

• Ceramic Flatpack (Package 316)

• Ceramic SOJ (Package 327)

• Ceramic LCC (Package 502)



Single +5V (±10%) Supply Operation

*This product is subject to change without notice.

The EDI88512CA is a 4 megabit Monolithic CMOS Static RAM.

The 32 pin DIP pinout adheres to the JEDEC evolutionary standard

for the four megabit device. All 32 pin packages are pin for pin

upgrades for the single chip enable 128K x 8, the EDI88128CS.

Pins 1 and 30 become the higher order addresses.

The 36 pin revolutionary pinout also adheres to the JEDEC

standard for the four megabit device. The center pin power and

ground pins help to reduce noise in high performance systems.

The 36 pin pinout also allows the user an upgrade path to the

future 2Mx8.

A Low Power version with Data Retention (EDI88512LPA) is

also available for battery backed applications. Military product is

available compliant to Appendix A of MIL-PRF-38535.

FIGURE 1 – PIN CONFIGURATION

I/O

0-7

-18

WE#

CS#

OE#

PIN DESCRIPTION

Data Inputs/Outputs

Address Inputs

Write Enables

Chip Selects

Output Enable

Power (+5V ±10%)

Ground

Not Connected

36 PIN

TOP VIEW

CS#

I/O0

I/O1

Vcc

Vss

I/O2

I/O3

WE#

36 pin

Revolutionary

A18

A17

A16

A15

OE#

I/O7

I/O6

Vss

Vcc

I/O5

I/O4

A14

A13

A12

A11

A10

A18

A16

A14

A12

I/O0

I/O1

I/O2

Vss

32 PIN

TOP VIEW

Vcc

A15

A17

WE#

A13

A11

OE#

A10

CS#

I/O7

I/O6

I/O5

I/O4

I/O3

BLOCK DIAGRAM

Memory Array

32 pin

Evolutionary

0-18

Address

Buffer

Address

Decoder

I/O

Circuits

I/O

0-7

WE#

CS#

OE#

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

February 2012

Rev. 14

Microsemi Corporation • (602) 437-1520 • www.microsemi.com

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