X24645V-2.7 datasheet, PDF - EEWORLD Datasheet

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X24645V-2.7: DescriptionEEPROM, 8KX8, Serial, CMOS, PDSO20, PLASTIC, TSSOP-20; Categorystorage storage; File Size313KB，18 Pages; ManufacturerIC Microsystems Sdn Bhd

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X24645V-2.7 Overview

EEPROM, 8KX8, Serial, CMOS, PDSO20, PLASTIC, TSSOP-20

X24645V-2.7 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	TSSOP
package instruction	TSSOP, TSSOP20,.25
Contacts	20
Reach Compliance Code	unknown
ECCN code	EAR99
Maximum clock frequency (fCLK)	0.1 MHz
Data retention time - minimum	100
Durability	100000 Write/Erase Cycles
I2C control byte	DDMMMMMR
JESD-30 code	R-PDSO-G20
JESD-609 code	e0
length	6.5 mm
memory density	65536 bit
Memory IC Type	EEPROM
memory width	8
Humidity sensitivity level	3
Number of functions	1
Number of terminals	20
word count	8192 words
character code	8000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	8KX8
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP20,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Parallel/Serial	SERIAL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3/5 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Serial bus type	I2C
Maximum standby current	0.000001 A
Maximum slew rate	0.003 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	4.4 mm
Maximum write cycle time (tWC)	10 ms
write protect	HARDWARE/SOFTWARE
Base Number Matches	1

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This X24645 device has been acquired by

IC MICROSYSTEMS from Xicor, Inc.

ICmic

IC MICROSYSTEMS

64K

X24645

8192 x 8 Bit

Advanced 2-Wire Serial E PROM with Block Lock

Protection

FEATURES

•

2.7V to 5.5V Power Supply

•

Low Power CMOS

—Active Read Current Less Than 1mA

—Active Write Current Less Than 3mA

—Standby Current Less Than 1∝A

•

Internally Organized 8192 x 8

•

New Programmable Block Lock Protection

—Software Write Protection

—Programmable hardware Write Protect

•

Block Lock (0, 1/4, 1/2, or all of the E

PROM

array)

DESCRIPTION

The X24645 is a CMOS 65,536-bit serial E PROM,

internally organized 8192 x 8. The X24645 features a

serial interface and software protocol allowing operation

on a simple two wire bus.

Two device select inputs (S

, S

) allow up to four

devices to share a common two wire bus.

A Write Protect Register at the highest address location,

1FFFh, provides three new write protection

features: Software Write Protect, Block Write Protect, and

Hardware Write Protect. The Software Write

•

2 Wire Serial Interface

•

Bidirectional Data Transfer Protocol

•

32 Byte Page Write Mode

Protect feature prevents any nonvolatile writes to the

X24645 until the WEL bit in the write protect register is

set. The Block Write Protection feature allows the user to

individually write protect four blocks of the array by

—Minimizes Total Write Time Per Byte

•

Self Timed Write Cycle

—Typical Write Cycle Time of 5ms

•

High Reliability

—Endurance: 100,000 Cycles

—Data Retention: 100 Years

•

Available Packages

—8-Lead PDIP

—8-Lead SOIC (JEDEC)

—14-Lead SOIC (JEDEC)

—20-Lead TSSOP

FUNCTIONAL DIAGRAM

programming two bits in the write protect register. The

Programmable Hardware Write Protect feature allows

the user to install the X24645 with WP tied to V

program the entire memory array in place, and then

enable the hardware write protection by programming a

WPEN bit in the write protect register. After this,

selected blocks of the array, including the write protect

as WP remains HIGH.

START CYCLE

H.V. GENERATION

TIMING &

CONTROL

SDA

START

STOP

WRITE PROTECT

LOGIC

CONTROL

LOGIC

SLAVE ADDRESS

SCL

+COMPARATOR

LOAD

INC

XDEC

E PROM

256 X 256

WORD

ADDRESS

COUNTER

R/W

YDEC

DATA REGISTER

OUT

ACK

2783 ILL F01

©Xicor,

1995, 1996 Patents Pending

2783-3.5 5/13/96 T1/C0/D0 NS

Characteristics subject to change without notice

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