ADVANCE
‡
512Mb: x4, x8, x16
SDRAM
SYNCHRONOUS
DRAM
FEATURES
• PC100- and PC133-compliant
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE, and Auto Refresh Modes
• Self Refresh Mode
• 64ms, 8,192-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
MT48LC128M4A2 – 32 Meg x 4 x 4 banks
MT48LC64M8A2 – 16 Meg x 8 x 4 banks
MT48LC32M16A2 – 8 Meg x 16 x 4 banks
For the latest data sheet, please refer to the Micron Web site:
www.micron.com/dramds
Pin Assignment (Top View)
54-Pin TSOP
x4 x8 x16
-
-
-
-
-
NC
x16 x8 x4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
-
-
-
-
-
NC
NC
DQ0
NC NC
DQ0 DQ1
NC NC
NC
DQ2
NC NC
DQ1 DQ3
OPTIONS
• Configurations
128 Meg x 4 (32 Meg x 4 x 4 banks)
64 Meg x 8 (16 Meg x 8 x 4 banks)
32 Meg x 16 (8 Meg x 16 x 4 banks)
• WRITE Recovery (
t
WR)
t
WR = “2 CLK”
1
• Plastic Package – OCPL
2
54-pin TSOP II (400 mil)
• Timing (Cycle Time)
7.5ns @ CL = 2 (PC133)
7.5ns @ CL = 3 (PC133)
• Self Refresh
Standard
Low power
• Operating Temperature
Commercial (0
o
C to +70
o
C)
MARKING
128M4
64M8
32M16
A2
TG
-7E
-75
None
L
None
-
NC
-
NC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
DD
DQ0
V
DD
Q
DQ1
DQ2
VssQ
DQ3
DQ4
V
DD
Q
DQ5
DQ6
VssQ
DQ7
V
DD
DQML
WE#
CAS#
RAS#
CS#
BA0
BA1
A10
A0
A1
A2
A3
V
DD
-
Vss
DQ15 DQ7
VssQ
-
DQ14
NC
DQ13 DQ6
V
DD
Q
-
DQ12
NC
DQ11 DQ5
VssQ
-
DQ10
NC
DQ9 DQ4
V
DD
Q
-
DQ8
NC
-
Vss
-
NC
DQMH DQM
-
CLK
CKE
-
A12
-
A11
-
A9
-
A8
-
A7
-
A6
-
A5
-
A4
-
Vss
-
-
NC
-
NC
DQ3
-
NC
NC
-
NC
DQ2
-
NC
-
-
DQM
-
-
-
-
-
-
-
-
-
-
-
NOTE:
The # symbol indicates signal is active LOW. A dash
(–) indicates x8 and x4 pin function is same as x16
pin function.
Configuration
Refresh Count
Row Addressing
Bank Addressing
128 Meg x 4
64 Meg x 8
32 Meg x 16
32 Meg x 4 x 4 banks 16 Meg x 8 x 4 banks 8 Meg x 16 x 4 banks
8K
8K
8K
8K (A0–A12)
8K (A0–A12)
8K (A0–A12)
4 (BA0, BA1)
4 (BA0, BA1)
4 (BA0, BA1)
2K (A0–A9, A11)
1K (A0–A9)
Column Addressing 4K (A0–A9, A11, A12)
NOTE:
1. Refer to Micron Technical Note TN-48-05.
2. Off-center parting line.
Part Number Example:
KEY TIMING PARAMETERS
SPEED
GRADE
-7E
-75
-7E
-75
CLOCK
ACCESS TIME SETUP
FREQUENCY CL = 2* CL = 3* TIME
143 MHz
133 MHz
133 MHz
100 MHz
–
–
5.4ns
6ns
5.4ns
5.4ns
–
–
1.5ns
1.5ns
1.5ns
1.5ns
HOLD
TIME
0.8ns
0.8ns
0.8ns
0.8ns
MT48LC32M16A2TG-75
512Mb SDRAM PART NUMBERS
PART NUMBER
MT48LC128M4A2TG
MT48LC64M8A2TG
MT48LC32M16A2TG
ARCHITECTURE
128 Meg x 4
64 Meg x 8
32 Meg x 16
*CL = CAS (READ) latency
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE
BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
ADVANCE
512Mb: x4, x8, x16
SDRAM
GENERAL DESCRIPTION
The 512Mb SDRAM is a high-speed CMOS, dynamic
random-access memory containing 536,870,912 bits. It is
internally configured as a quad-bank DRAM with a syn-
chronous interface (all signals are registered on the posi-
tive edge of the clock signal, CLK). Each of the x4’s
134,217,728-bit banks is organized as 8,192 rows by 4,096
columns by 4 bits. Each of the x8’s 134,217,728-bit banks
is organized as 8,192 rows by 2,048 columns by 8 bits.
Each of the x16’s 134,217,728-bit banks is organized as
8,192 rows by 1,024 columns by 16 bits.
Read and write accesses to the SDRAM are burst ori-
ented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an AC-
TIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed (BA0, BA1 select the bank; A0-A12
select the row). The address bits registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
The SDRAM provides for programmable READ or
WRITE burst lengths of 1, 2, 4, or 8 locations, or the full
page, with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst se-
quence.
The 512Mb SDRAM uses an internal pipelined archi-
tecture to achieve high-speed operation. This architec-
ture is compatible with the 2n rule of prefetch architec-
tures, but it also allows the column address to be changed
on every clock cycle to achieve a high-speed, fully ran-
dom access. Precharging one bank while accessing one of
the other three banks will hide the precharge cycles and
provide seamless, high-speed, random-access operation.
The 512Mb SDRAM is designed to operate at 3.3V. An
auto refresh mode is provided, along with a power-sav-
ing, power-down mode. All inputs and outputs are LVTTL-
compatible.
SDRAMs offer substantial advances in DRAM operat-
ing performance, including the ability to synchronously
burst data at a high data rate with automatic column-
address generation, the ability to interleave between in-
ternal banks to hide precharge time and the capability to
randomly change column addresses on each clock cycle
during a burst access.
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
ADVANCE
512Mb: x4, x8, x16
SDRAM
TABLE OF CONTENTS
Functional
Block Diagram – 128 Meg x 4 ....................
Functional Block Diagram – 64 Meg x 8 ...................
Functional Block Diagram – 32 Meg x 16 .................
Pin Descriptions ...........................................................
Functional Description
...............................................
Initialization ............................................................
Register Definition ..................................................
Mode Register ....................................................
Burst Length .................................................
Burst Type ....................................................
CAS Latency .................................................
Operating Mode ...........................................
Write Burst Mode .........................................
Commands
....................................................................
Truth Table 1 (Commands and DQM Operation)
............
Command Inhibit ...................................................
No Operation (NOP) ...............................................
Load Mode Register ................................................
Active .......................................................................
Read .......................................................................
Write .......................................................................
Precharge .................................................................
Auto Precharge ........................................................
Burst Terminate ......................................................
Auto Refresh ............................................................
Self Refresh ..............................................................
Operation
......................................................................
Bank/Row Activation ..............................................
Reads .......................................................................
Writes .......................................................................
Precharge .................................................................
Power-Down ............................................................
Clock Suspend .........................................................
4
5
6
7
8
8
8
8
8
9
10
10
10
11
11
12
12
12
12
12
12
12
12
13
13
13
14
14
16
21
23
23
24
Burst Read/Single Write .........................................
Concurrent Auto Precharge ...................................
Truth Table 2 (CKE)
.....................................................
Truth Table 3 (Current State, Same Bank)
......................
Truth Table 4 (Current State, Different Bank)
.................
Absolute Maximum Ratings ........................................
DC Electrical Characteristics and Operating
Conditions ................................................................
I
DD
Specifications and Conditions ..............................
Capacitance ...................................................................
Timing Waveforms
Initialize and Load Mode Register .........................
Power-Down Mode .................................................
Clock Suspend Mode ..............................................
Auto Refresh Mode .................................................
Self Refresh Mode ...................................................
Reads
Read – Without Auto Precharge .......................
Read – With Auto Precharge .............................
Single Read – Without Auto Precharge ............
Single Read – With Auto Precharge .................
Alternating Bank Read Accesses ......................
Read – Full-Page Burst ......................................
Read – DQM Operation ....................................
Writes
Write – Without Auto Precharge ......................
Write – With Auto Precharge ............................
Single Write – Without Auto Precharge ...........
Single Write – With Auto Precharge .................
Alternating Bank Write Accesses .....................
Write – Full-Page Burst .....................................
Write – DQM Operation ....................................
24
25
27
28
30
32
32
32
33
AC Electrical Characteristics
(Timing Table) ............ 33
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
ADVANCE
512Mb: x4, x8, x16
SDRAM
FUNCTIONAL BLOCK DIAGRAM
128 Meg x 4 SDRAM
CKE
CLK
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
COMMAND
DECODE
MODE REGISTER
REFRESH 13
COUNTER
12
13
ROW-
ADDRESS
MUX
13
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
8192
BANK0
MEMORY
ARRAY
(8,192 x 4,096 x 4)
1
1
DQM
SENSE AMPLIFIERS
4
8192
DATA
OUTPUT
REGISTER
2
A0-A12,
BA0, BA1
ADDRESS
REGISTER
BANK
CONTROL
LOGIC
15
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
4
4096
(x4)
DATA
INPUT
REGISTER
4
DQ0-
DQ3
2
COLUMN
DECODER
COLUMN-
ADDRESS
COUNTER/
LATCH
12
12
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
ADVANCE
512Mb: x4, x8, x16
SDRAM
FUNCTIONAL BLOCK DIAGRAM
64 Meg x 8 SDRAM
CKE
CLK
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
COMMAND
DECODE
MODE REGISTER
REFRESH 13
COUNTER
12
13
ROW-
ADDRESS
MUX
13
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
8192
BANK0
MEMORY
ARRAY
(8,192 x 2,048 x 8)
1
1
DQM
SENSE AMPLIFIERS
8
8192
DATA
OUTPUT
REGISTER
2
A0-A12,
BA0, BA1
ADDRESS
REGISTER
BANK
CONTROL
LOGIC
15
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
8
2048
(x8)
DATA
INPUT
REGISTER
8
DQ0-
DQ7
2
COLUMN
DECODER
COLUMN-
ADDRESS
COUNTER/
LATCH
11
11
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
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