MT48LC128M4A2TG-75 datasheet, PDF

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MT48LC128M4A2TG-75: DescriptionSynchronous DRAM, 128MX4, 5.4ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54; Categorystorage storage; File Size2MB，55 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/

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MT48LC128M4A2TG-75 Overview

Synchronous DRAM, 128MX4, 5.4ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54

MT48LC128M4A2TG-75 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Micron Technology
Parts packaging code	TSOP2
package instruction	0.400 INCH, PLASTIC, TSOP2-54
Contacts	54
Reach Compliance Code	not_compliant
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	5.4 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	133 MHz
I/O type	COMMON
interleaved burst length	1,2,4,8
JESD-30 code	R-PDSO-G54
JESD-609 code	e0
length	22.22 mm
memory density	536870912 bit
Memory IC Type	SYNCHRONOUS DRAM
memory width	4
Number of functions	1
Number of ports	1
Number of terminals	54
word count	134217728 words
character code	128000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128MX4
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Encapsulate equivalent code	TSOP54,.46,32
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Peak Reflow Temperature (Celsius)	235
power supply	3.3 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	1.2 mm
self refresh	YES
Continuous burst length	1,2,4,8,FP
Maximum standby current	0.0035 A
Maximum slew rate	0.255 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	10.16 mm

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ADVANCE

‡

512Mb: x4, x8, x16

SDRAM

SYNCHRONOUS

DRAM

FEATURES

• PC100- and PC133-compliant

• Fully synchronous; all signals registered on positive

edge of system clock

• Internal pipelined operation; column address can be

changed every clock cycle

• Internal banks for hiding row access/precharge

• Programmable burst lengths: 1, 2, 4, 8, or full page

• Auto Precharge, includes CONCURRENT AUTO

PRECHARGE, and Auto Refresh Modes

• Self Refresh Mode

• 64ms, 8,192-cycle refresh

• LVTTL-compatible inputs and outputs

• Single +3.3V ±0.3V power supply

MT48LC128M4A2 – 32 Meg x 4 x 4 banks

MT48LC64M8A2 – 16 Meg x 8 x 4 banks

MT48LC32M16A2 – 8 Meg x 16 x 4 banks

For the latest data sheet, please refer to the Micron Web site:

www.micron.com/dramds

Pin Assignment (Top View)

54-Pin TSOP

x4 x8 x16

x16 x8 x4

DQ0

NC NC

DQ0 DQ1

NC NC

DQ2

NC NC

DQ1 DQ3

OPTIONS

• Configurations

128 Meg x 4 (32 Meg x 4 x 4 banks)

64 Meg x 8 (16 Meg x 8 x 4 banks)

32 Meg x 16 (8 Meg x 16 x 4 banks)

• WRITE Recovery (

WR)

WR = “2 CLK”

• Plastic Package – OCPL

54-pin TSOP II (400 mil)

• Timing (Cycle Time)

7.5ns @ CL = 2 (PC133)

7.5ns @ CL = 3 (PC133)

• Self Refresh

Standard

Low power

• Operating Temperature

Commercial (0

C to +70

MARKING

128M4

64M8

32M16

-7E

-75

None

DQ0

DQ1

DQ2

VssQ

DQ3

DQ4

DQ5

DQ6

VssQ

DQ7

DQML

WE#

CAS#

RAS#

CS#

BA0

BA1

A10

Vss

DQ15 DQ7

VssQ

DQ14

DQ13 DQ6

DQ12

DQ11 DQ5

VssQ

DQ10

DQ9 DQ4

DQ8

Vss

DQMH DQM

CLK

CKE

A12

A11

Vss

DQ3

DQ2

DQM

NOTE:

The # symbol indicates signal is active LOW. A dash

(–) indicates x8 and x4 pin function is same as x16

pin function.

Configuration

Refresh Count

Row Addressing

Bank Addressing

128 Meg x 4

64 Meg x 8

32 Meg x 16

32 Meg x 4 x 4 banks 16 Meg x 8 x 4 banks 8 Meg x 16 x 4 banks

8K (A0–A12)

4 (BA0, BA1)

2K (A0–A9, A11)

1K (A0–A9)

Column Addressing 4K (A0–A9, A11, A12)

NOTE:

1. Refer to Micron Technical Note TN-48-05.

2. Off-center parting line.

Part Number Example:

KEY TIMING PARAMETERS

SPEED

GRADE

-7E

-75

-7E

-75

CLOCK

ACCESS TIME SETUP

FREQUENCY CL = 2* CL = 3* TIME

143 MHz

133 MHz

100 MHz

–

5.4ns

6ns

5.4ns

–

1.5ns

HOLD

TIME

0.8ns

MT48LC32M16A2TG-75

512Mb SDRAM PART NUMBERS

PART NUMBER

MT48LC128M4A2TG

MT48LC64M8A2TG

MT48LC32M16A2TG

ARCHITECTURE

128 Meg x 4

64 Meg x 8

32 Meg x 16

*CL = CAS (READ) latency

512Mb: x4, x8, x16 SDRAM

512MSDRAM_D.p65 – Rev. D; Pub 1/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE

BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.

MT48LC128M4A2TG-75 Related Products

	MT48LC128M4A2TG-75	MT48LC32M16A2TG-7E	MT48LC64M8A2TG-75	MT48LC64M8A2TG-7E
Description	Synchronous DRAM, 128MX4, 5.4ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54	Synchronous DRAM, 32MX16, 5.4ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54	Synchronous DRAM, 64MX8, 5.4ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54	Synchronous DRAM, 64MX8, 5.4ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54
Is it lead-free?	Contains lead	Contains lead	Contains lead	Contains lead
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible
Parts packaging code	TSOP2	TSOP2	TSOP2	TSOP2
package instruction	0.400 INCH, PLASTIC, TSOP2-54	TSOP2, TSOP54,.46,32	0.400 INCH, PLASTIC, TSOP2-54	0.400 INCH, PLASTIC, TSOP2-54
Contacts	54	54	54	54
Reach Compliance Code	not_compliant	not_compliant	not_compliant	not_compliant
ECCN code	EAR99	EAR99	EAR99	EAR99
Maker	Micron Technology	-	Micron Technology	Micron Technology
access mode	FOUR BANK PAGE BURST	-	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
Maximum access time	5.4 ns	-	5.4 ns	5.4 ns
Other features	AUTO/SELF REFRESH	-	AUTO/SELF REFRESH	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	133 MHz	-	133 MHz	143 MHz
I/O type	COMMON	-	COMMON	COMMON
interleaved burst length	1,2,4,8	-	1,2,4,8	1,2,4,8
JESD-30 code	R-PDSO-G54	-	R-PDSO-G54	R-PDSO-G54
JESD-609 code	e0	-	e0	e0
length	22.22 mm	-	22.22 mm	22.22 mm
memory density	536870912 bit	-	536870912 bit	536870912 bit
Memory IC Type	SYNCHRONOUS DRAM	-	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM
memory width	4	-	8	8
Number of functions	1	-	1	1
Number of ports	1	-	1	1
Number of terminals	54	-	54	54
word count	134217728 words	-	67108864 words	67108864 words
character code	128000000	-	64000000	64000000
Operating mode	SYNCHRONOUS	-	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	-	70 °C	70 °C
organize	128MX4	-	64MX8	64MX8
Output characteristics	3-STATE	-	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSOP2	-	TSOP2	TSOP2
Encapsulate equivalent code	TSOP54,.46,32	-	TSOP54,.46,32	TSOP54,.46,32
Package shape	RECTANGULAR	-	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE	-	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE
Peak Reflow Temperature (Celsius)	235	-	235	235
power supply	3.3 V	-	3.3 V	3.3 V
Certification status	Not Qualified	-	Not Qualified	Not Qualified
refresh cycle	8192	-	8192	8192
Maximum seat height	1.2 mm	-	1.2 mm	1.2 mm
self refresh	YES	-	YES	YES
Continuous burst length	1,2,4,8,FP	-	1,2,4,8,FP	1,2,4,8,FP
Maximum standby current	0.0035 A	-	0.0035 A	0.0035 A
Maximum slew rate	0.255 mA	-	0.255 mA	0.255 mA
Maximum supply voltage (Vsup)	3.6 V	-	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3 V	-	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	-	3.3 V	3.3 V
surface mount	YES	-	YES	YES
technology	CMOS	-	CMOS	CMOS
Temperature level	COMMERCIAL	-	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	-	GULL WING	GULL WING
Terminal pitch	0.8 mm	-	0.8 mm	0.8 mm
Terminal location	DUAL	-	DUAL	DUAL
Maximum time at peak reflow temperature	30	-	30	30
width	10.16 mm	-	10.16 mm	10.16 mm

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