GS8170LW36C-250 datasheet, PDF

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GS8170LW36C-250: DescriptionStandard SRAM, 512KX36, 2.1ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209; Categorystorage storage; File Size884KB，27 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/

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GS8170LW36C-250 Overview

Standard SRAM, 512KX36, 2.1ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209

GS8170LW36C-250 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	BGA
package instruction	14 X 22 MM, 1 MM PITCH, BGA-209
Contacts	209
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
Maximum access time	2.1 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B209
length	22 mm
memory density	18874368 bit
Memory IC Type	STANDARD SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	209
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512KX36
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	1.7 mm
Maximum supply voltage (Vsup)	1.95 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm
Base Number Matches	1

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GS8170LW36/72C-333/300/250/200

209-Bump BGA

Commercial Temp

Industrial Temp

Features

• Late Write mode, Pipelined Read mode

• JEDEC-standard SigmaRAM

™

pinout and package

• 1.8 V +150/–100 mV core power supply

• 1.8 V CMOS Interface

• ZQ controlled user-selectable output drive strength

• Dual Cycle Deselect

• Burst Read and Write option

• Fully coherent read and write pipelines

• Echo Clock outputs track data output drivers

• Byte write operation (9-bit bytes)

• 2 user-programmable chip enable inputs

• IEEE 1149.1 JTAG-compliant Serial Boundary Scan

• 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package

• Pin-compatible with future 36Mb, 72Mb, and 144Mb

devices

18Mb

1x1Lp CMOS I/O

Late Write SigmaRAM™

Functional Description

200 MHz–333 MHz

1.8 V V

1.8 V I/O

SigmaRAM Family Overview

GS8170LW36/72 SigmaRAMs are built in compliance with

the SigmaRAM pinout standard for synchronous SRAMs.

They are 18,874,368-bit (18Mb) SRAMs. This family of wide,

very low voltage CMOS I/O SRAMs is designed to operate at

the speeds needed to implement economical high performance

networking systems.

Bottom View

209-Bump, 14 mm x 22 mm BGA

1 mm Bump Pitch, 11 x 19 Bump Array

Because SigmaRAMs are synchronous devices, address data

inputs and read/write control inputs are captured on the rising

edge of the input clock. Write cycles are internally self-timed

and initiated by the rising edge of the clock input. This feature

eliminates complex off-chip write pulse generation required by

asynchronous SRAMs and simplifies input signal timing.

RAMs support pipelined reads utilizing a rising-edge-

triggered output register. They also utilize a Dual Cycle

Deselect (DCD) output deselect protocol.

RAMs are offered in a number of configurations including

Late Write, Double Late Write, and Double Data Rate (DDR).

The logical differences between the protocols employed by

these RAMs mainly involve various approaches to write

cueing and data transfer rates. The

RAM

™

family standard

allows a user to implement the interface protocol best suited to

the task at hand.

RAMs are implemented with high performance CMOS

technology and are packaged in a 209-bump BGA.

Parameter Synopsis

Key Fast Bin Specs

Cycle Time

Access Time

Symbol

tKHKH

tKHQV

- 333

3.0 ns

1.6 ns

Rev: 2.03 1/2005

1/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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