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CD74AC280EE4

Description
Parity Generator/Checker, AC Series, 9-Bit, Complementary Output, CMOS, PDIP14, ROHS COMPLIANT, PLASTIC, DIP-14
Categorylogic    logic   
File Size590KB,13 Pages
ManufacturerRochester Electronics
Websitehttps://www.rocelec.com/
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CD74AC280EE4 Overview

Parity Generator/Checker, AC Series, 9-Bit, Complementary Output, CMOS, PDIP14, ROHS COMPLIANT, PLASTIC, DIP-14

CD74AC280EE4 Parametric

Parameter NameAttribute value
package instructionDIP,
Reach Compliance Codeunknown
Other featuresODD/EVEN PARITY GENERATOR
seriesAC
JESD-30 codeR-PDIP-T14
length19.305 mm
Logic integrated circuit typePARITY GENERATOR/CHECKER
Number of digits9
Number of functions1
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Output polarityCOMPLEMENTARY
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
propagation delay (tpd)263 ns
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)1.5 V
Nominal supply voltage (Vsup)3.3 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
width7.62 mm
Base Number Matches1
CD54/74AC280,
CD54/74ACT280
Data sheet acquired from Harris Semiconductor
SCHS250A
August 1998 - Revised May 2000
9-Bit Odd/Even Parity Generator/Checker
data inputs is HIGH. Odd parity is indicated (∑O output is
HIGH) when an odd number of data inputs is HIGH. Parity
checking for words larger than nine bits can be accom-
plished by tying the
∑E
output to any input of an additional
’AC280, ’ACT280 parity checker.
Features
• Buffered Inputs
• Typical Propagation Delay
- 10ns at V
CC
= 5V, T
A
= 25
o
C, C
L
= 50pF
• Exceeds 2kV ESD Protection per MIL-STD-883,
Method 3015
• SCR-Latchup-Resistant CMOS Process and Circuit
Design
• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption
• Balanced Propagation Delays
• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply
±24mA
Output Drive Current
- Fanout to 15 FAST™ ICs
- Drives 50Ω Transmission Lines
Ordering Information
PART
NUMBER
CD54AC280F3A
CD74AC280E
CD74AC280M
CD54ACT280F3A
CD74ACT280E
CD74ACT280M
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all elec-
trical specifications. Please contact your local TI sales office or cus-
tomer service for ordering information.
TEMP.
RANGE (
o
C)
-55 to 125
0 to 70
o
C, -40 to 85,
-55 to 125
0 to 70
o
C, -40 to 85,
-55 to 125
-55 to 125
0 to 70
o
C, -40 to 85,
-55 to 125
0 to 70
o
C, -40 to 85,
-55 to 125
PACKAGE
14 Ld CERDIP
14 Ld PDIP
14 Ld SOIC
14 Ld CERDIP
14 Ld PDIP
14 Ld SOIC
Description
The ’AC280 and ’ACT280 are 9-bit odd/even parity genera-
tor/checkers that utilize Advanced CMOS Logic technology.
Both even and odd parity outputs are available for checking
or generating parity for words up to nine bits long. Even par-
ity is indicated (∑E output is HIGH) when an even number of
Pinout
CD54AC280, CD54ACT280
(CERDIP)
CD74AC280, CD74ACT280
(PDIP, SOIC)
TOP VIEW
Functional Diagram
I0
I1
8
9
10
5
11
12
I6 1
I7 2
NC 3
I8 4
∑E
5
∑O
6
GND 7
14 V
CC
13 I5
12 I4
11 I3
I2
I3
I4
I5
EVEN
6
13
1
2
4
ODD
10 I2
9 I1
8 I0
I6
I7
I8
GND = 7
V
CC
= 14
NC = 3
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.
Copyright
©
2000, Texas Instruments Incorporated
1

CD74AC280EE4 Related Products

CD74AC280EE4 CD74AC280M96E4 CD74AC280ME4
Description Parity Generator/Checker, AC Series, 9-Bit, Complementary Output, CMOS, PDIP14, ROHS COMPLIANT, PLASTIC, DIP-14 Parity Generator/Checker, AC Series, 9-Bit, Complementary Output, CMOS, PDSO14, GREEN, PLASTIC, MS-012AB, SOIC-14 Parity Generator/Checker, AC Series, 9-Bit, Complementary Output, CMOS, PDSO14, GREEN, PLASTIC, MS-012AB, SOIC-14
package instruction DIP, SOP, SOP,
Reach Compliance Code unknown unknown unknown
Other features ODD/EVEN PARITY GENERATOR ODD/EVEN PARITY GENERATOR ODD/EVEN PARITY GENERATOR
series AC AC AC
JESD-30 code R-PDIP-T14 R-PDSO-G14 R-PDSO-G14
length 19.305 mm 8.65 mm 8.65 mm
Logic integrated circuit type PARITY GENERATOR/CHECKER PARITY GENERATOR/CHECKER PARITY GENERATOR/CHECKER
Number of digits 9 9 9
Number of functions 1 1 1
Number of terminals 14 14 14
Maximum operating temperature 125 °C 125 °C 125 °C
Minimum operating temperature -55 °C -55 °C -55 °C
Output polarity COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code DIP SOP SOP
Package shape RECTANGULAR RECTANGULAR RECTANGULAR
Package form IN-LINE SMALL OUTLINE SMALL OUTLINE
propagation delay (tpd) 263 ns 263 ns 263 ns
Maximum seat height 5.08 mm 1.75 mm 1.75 mm
Maximum supply voltage (Vsup) 5.5 V 5.5 V 5.5 V
Minimum supply voltage (Vsup) 1.5 V 1.5 V 1.5 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V 3.3 V
surface mount NO YES YES
technology CMOS CMOS CMOS
Temperature level MILITARY MILITARY MILITARY
Terminal form THROUGH-HOLE GULL WING GULL WING
Terminal pitch 2.54 mm 1.27 mm 1.27 mm
Terminal location DUAL DUAL DUAL
width 7.62 mm 3.9 mm 3.9 mm
Base Number Matches 1 1 1
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