SYN10E137JCTR datasheet, PDF - EEWORLD Datasheet

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SYN10E137JCTR: Description10E SERIES, ASYN POSITIVE EDGE TRIGGERED 8-BIT UP BINARY COUNTER, PQCC28, PLASTIC, LCC-28; Categorylogic logic; File Size65KB，5 Pages; ManufacturerMicrel ( Microchip ); Websitehttps://www.microchip.com

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SYN10E137JCTR Overview

10E SERIES, ASYN POSITIVE EDGE TRIGGERED 8-BIT UP BINARY COUNTER, PQCC28, PLASTIC, LCC-28

SYN10E137JCTR Parametric

Parameter Name	Attribute value
Parts packaging code	QLCC
package instruction	QCCJ,
Contacts	28
Reach Compliance Code	unknown
Counting direction	UP
series	10E
JESD-30 code	S-PQCC-J28
length	11.48 mm
Load/preset input	YES
Logic integrated circuit type	BINARY COUNTER
Operating mode	ASYNCHRONOUS
Number of digits	8
Number of functions	1
Number of terminals	28
Maximum operating temperature	85 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Package shape	SQUARE
Package form	CHIP CARRIER
propagation delay (tpd)	4.8 ns
Certification status	Not Qualified
Maximum seat height	4.57 mm
surface mount	YES
technology	ECL
Temperature level	OTHER
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Trigger type	POSITIVE EDGE
width	11.48 mm
minfmax	1800 MHz
Base Number Matches	1

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Micrel, Inc.

8-BIT RIPPLE

COUNTER

SY10E137

SY100E137

SY10E137

SY100E137

FEATURES

1.8GHz min. count frequency

Extended 100E V

range of –4.2V to –5.5V

Synchronous and asynchronous enable pins

Differential clock input and data output pins

output for single-ended use

Asynchronous Master Reset

DESCRIPTION

The SY10/100E137 are very high speed binary ripple

counters. The two least significant bits were designed

with very fast edge rates, while the more significant bits

maintain standard ECLinPS output edge rates. This allows

the counters to operate at very high frequencies, while

maintaining a moderate power dissipation level.

The devices are ideally suited for multiple frequency

clock generation, as well as for counters in high-

performance ATE time measurement boards.

Both asynchronous and synchronous enables are

available to maximize the device's flexibility for various

applications. The asynchronous enable input, A_Start,

when asserted, enables the counter while overriding any

synchronous enable signals. The E137 features XOR'ed

enable inputs, EN

and EN

, which are synchronous to

the CLK input. When only one synchronous enable is

asserted, the counter becomes disabled on the next CLK

transition. All outputs remain in the previous state poised

for the other synchronous enable or A_Start to be

asserted in order to re-enable the counter. Asserting

both synchronous enables causes the counter to become

enabled on the next transition of the CLK. EN

(or EN

)

and CLK edges are coincident. Sufficient delay has been

inserted in the CLK path (to compensate for the XOR

gate delay and the internal D-flip-flop set-up time) to

ensure that the synchronous enable signal is clocked

correctly; hence, the counter is disabled.

The E137 can also be driven single-endedly utilizing

the V

output supply as the voltage reference for the

CLK input signal. If a single-ended signal is to be used,

the V

pin should be connected to the CLK input and

bypassed to ground via a 0.01µF capacitor. V

can

only source/sink 0.5mA; therefore, it should be used as

a switching reference for the E137 only.

All input pins left open will be pulled LOW via an input

pull-down resistor. Therefore, do not leave the differential

CLK inputs open. Doing so causes the current source

transistor of the input clock gate to become saturated,

thus upsetting the internal bias regulators and

jeopardizing the stability of the device.

The asynchronous Master Reset resets the counter to

an all zero state upon assertion.

Internal 75K

Ω

input pull-down resistors

Available in 28-pin PLCC packge

PIN NAMES

CLK, CLK

–Q

, Q

–Q

A_Start

, EN

CCO

Function

Differential Clock Inputs

Differential Q Outputs

Asynchronous Enable Input

Synchronous Enable Inputs

Asynchronous Master Reset

Switching Reference Output

to Output

M9999-032006

hbwhelp@micrel.com or (408) 955-1690

Rev.: E

Amendment: /0

Issue Date: March 2006

SYN10E137JCTR Related Products

	SYN10E137JCTR	SYN100E137JCTR
Description	10E SERIES, ASYN POSITIVE EDGE TRIGGERED 8-BIT UP BINARY COUNTER, PQCC28, PLASTIC, LCC-28	100E SERIES, ASYN POSITIVE EDGE TRIGGERED 8-BIT UP BINARY COUNTER, PQCC28, PLASTIC, LCC-28
Parts packaging code	QLCC	QLCC
package instruction	QCCJ,	QCCJ,
Contacts	28	28
Reach Compliance Code	unknown	compliant
Counting direction	UP	UP
series	10E	100E
JESD-30 code	S-PQCC-J28	S-PQCC-J28
length	11.48 mm	11.48 mm
Load/preset input	YES	YES
Logic integrated circuit type	BINARY COUNTER	BINARY COUNTER
Operating mode	ASYNCHRONOUS	ASYNCHRONOUS
Number of digits	8	8
Number of functions	1	1
Number of terminals	28	28
Maximum operating temperature	85 °C	85 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QCCJ	QCCJ
Package shape	SQUARE	SQUARE
Package form	CHIP CARRIER	CHIP CARRIER
propagation delay (tpd)	4.8 ns	4.8 ns
Certification status	Not Qualified	Not Qualified
Maximum seat height	4.57 mm	4.57 mm
surface mount	YES	YES
technology	ECL	ECL
Temperature level	OTHER	OTHER
Terminal form	J BEND	J BEND
Terminal pitch	1.27 mm	1.27 mm
Terminal location	QUAD	QUAD
Trigger type	POSITIVE EDGE	POSITIVE EDGE
width	11.48 mm	11.48 mm
minfmax	1800 MHz	1800 MHz
Base Number Matches	1	1

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