S71WSxxxJ based MCPs
Stacked Multi-Chip Product (MCP)
128/64 Megabit (8M/4M x 16-bit) CMOS 1.8 Volt-only,
Simultaneous Read/Write, Burst Mode Flash Memory
with CosmoRAM
ADVANCE
DATASHEET
Distinctive Characteristics
MCP Features
Power supply voltage of 1.7 to 1.95V
Speed: 66MHz
Packages
— 8 x 11.6mm, 84 ball FBGA
— 7 x 9mm, 80-ball FBGA
Operating Temperature
— –25°C to +85°C
— –40°C to +85°C
General Description
The S71WS series is a product line of stacked Multi-Chip Product (MCP) packages
and consists of:
One or more flash memory die
pSRAM
The products covered by this document are listed in the table below. For details
about their specifications, please refer to the individual constituent datasheets for
further details:
Flash Memory Density
256Mb
64Mb
pSRAM
Density
32Mb
16Mb
S71WS256JC0
128Mb
S71WS128JC0
S71WS128JB0
S71WS128JA0
S71WS064JB0
S71WS064JA0
64Mb
Publication Number
S71WS256/128/064J_CS
Revision
A
Amendment
0
Issue Date
October 27, 2004
Product Selector Guide
Device-Model#
S71WS064JA0-2Y
S71WS064JB0-2Y
S71WS128JA0-AY
S71WS128JB0-AY
S71WS128JC0-AY
S71WS256JC0-TY
256Mb
128Mb
64Mb
Flash Speed pSRAM Speed
Flash Density pSRAM Density
(MHz)
(MHz/ns)
64Mb
16Mb
Supplier
Cosmo RAM
Cosmo RAM
32Mb
66
66/70
Cosmo RAM
Cosmo RAM
Cosmo RAM
Cosmo RAM
FTA084
TLA084
Package
TLC080
Availability
Status
Advanced
Advanced
Preliminary
Preliminary
Preliminary
Advanced
2
S71WSxxxJ based MCPs
S71WS256/128/064J_CSA0 October 27, 2004
A d v a n c e
I n f o r m a t i o n
S71WSxxxJ based MCPs
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . 1
MCP Features ........................................................................................................ 1
Automatic Sleep Mode ......................................................................................41
RESET#: Hardware Reset Input .................................................................41
Output Disable Mode ...................................................................................42
Figure 1. Temporary Sector Unprotect Operation ................... 42
Figure 2. In-System Sector Protection/Sector Unprotection
Algorithms........................................................................ 43
Table 7. SecSi™ Sector Addresses ...................................... 44
General Description . . . . . . . . . . . . . . . . . . . . . . . . 1
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .2
Connection Diagram (CosmoRAM Type-based) . .7
Special Handling Instructions For FBGA Package ...................................8
Connection Diagram (CosmoRAM Type-based) . .9
Special Handling Instructions For FBGA Package ................................. 10
Lookahead Connection Diagram . . . . . . . . . . . . . 11
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 12
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 13
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 16
TLA084—84-ball Fine-Pitch Ball Grid Array (FBGA)
8 x 11.6 mm Package ........................................................................................... 16
FTA084—84-ball Fine-Pitch Ball Grid Array (FBGA)
8 x 11.6 mm Package ............................................................................................17
TLC080—80-ball Fine-Pitch Ball Grid Array
(FBGA) 7 x 9 mm Package ............................................................................... 18
SecSi™ Sector Protection Bit ...................................................................... 45
Hardware Data Protection ......................................................................... 45
Write Protect (WP#) ....................................................................................... 45
Low V
CC
Write Inhibit ................................................................................. 46
Write Pulse “Glitch” Protection ...............................................................46
Logical Inhibit ...................................................................................................46
Power-Up Write Inhibit ...............................................................................46
Common Flash Memory Interface (CFI) . . . . . . . 47
Table 8. CFI Query Identification String ................................ 47
Table 9. System Interface String ......................................... 48
Table 10. Device Geometry Definition................................... 48
Table 11. Primary Vendor-Specific Extended Query ................ 49
Table 12. WS128J Sector Address Table ............................... 50
Table 13. WS064J Sector Address Table ............................... 58
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 64
Reading Array Data ...........................................................................................64
Set Configuration Register Command Sequence .....................................64
Figure 3. Synchronous/Asynchronous State Diagram.............. 65
S29WS128/064J
General Description . . . . . . . . . . . . . . . . . . . . . . . . 22
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .24
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Block Diagram of Simultaneous
Operation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Input/Output Descriptions . . . . . . . . . . . . . . . . . . .26
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 27
Table 1. Device Bus Operations .......................................... 27
Read Mode Setting ......................................................................................... 65
Programmable Wait State Configuration ............................................... 65
Table 14. Programmable Wait State Settings ......................... 66
Standard wait-state Handshaking Option ...............................................66
Table 15. Wait States for Standard wait-state Handshaking .... 66
Read Mode Configuration ...........................................................................66
Table 16. Read Mode Settings ............................................. 67
VersatileIO™ (V
IO
) Control .............................................................................27
Requirements for Asynchronous Read Operation (Non-Burst) ..........27
Requirements for Synchronous (Burst) Read Operation ...................... 28
8-, 16-, and 32-Word Linear Burst with Wrap Around ..................... 29
Table 2. Burst Address Groups ............................................ 29
Burst Active Clock Edge Configuration .................................................. 67
RDY Configuration ........................................................................................ 67
Table 17. Configuration Register .......................................... 68
Configuration Register ..................................................................................... 29
Handshaking ......................................................................................................... 29
Simultaneous Read/Write Operations with Zero Latency ................... 30
Writing Commands/Command Sequences ................................................ 30
Accelerated Program Operation .................................................................. 30
Autoselect Mode ..................................................................................................31
Table 3. Autoselect Codes (High Voltage Method) ................. 32
Reset Command .................................................................................................68
Autoselect Command Sequence ....................................................................68
Enter SecSi™ Sector/Exit SecSi™ Sector Command Sequence .............69
Program Command Sequence ........................................................................70
Unlock Bypass Command Sequence ........................................................70
Figure 4. Program Operation ............................................... 71
Chip Erase Command Sequence .................................................................... 71
Sector Erase Command Sequence ................................................................ 72
Erase Suspend/Erase Resume Commands .................................................. 73
Figure 5. Erase Operation ................................................... 74
Sector/Sector Block Protection and Unprotection ..................................32
Table 4. S29WS128/064J_MCP Boot Sector/Sector Block Addresses
for Protection/Unprotection ................................................. 32
Table 5. S29WS064J Boot Sector/Sector Block Addresses for
Protection/Unprotection ..................................................... 34
Sector Protection ...........................................................................................36
Persistent Sector Protection ...........................................................................36
Persistent Protection Bit (PPB) ..................................................................37
Persistent Protection Bit Lock (PPB Lock) .............................................37
Dynamic Protection Bit (DYB) ...................................................................37
Table 6. Sector Protection Schemes ..................................... 38
Persistent Sector Protection Mode Locking Bit ........................................39
Password Protection Mode .............................................................................39
Password and Password Mode Locking Bit ................................................39
64-bit Password .................................................................................................. 40
Persistent Protection Bit Lock ....................................................................... 40
Standby Mode ...................................................................................................... 40
Password Program Command ....................................................................... 74
Password Verify Command ............................................................................. 74
Password Protection Mode Locking Bit Program Command .............. 75
Persistent Sector Protection Mode Locking Bit Program Command 75
SecSi™ Sector Protection Bit Program Command ................................... 75
PPB Lock Bit Set Command ............................................................................ 75
DPB Write/Erase/Status Command ............................................................. 76
Password Unlock Command .......................................................................... 76
PPB Program Command .................................................................................. 76
All PPB Erase Command .................................................................................. 77
PPB Status Command ....................................................................................... 77
PPB Lock Bit Status Command ...................................................................... 77
Command Definitions .......................................................................................78
Table 18. Command Definitions .......................................... 78
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 81
DQ7: Data# Polling .............................................................................................81
Figure 6. Data# Polling Algorithm ........................................ 82
October 27, 2004 S71WS256/128/064J_CSA0
3
A d v a n c e
I n f o r m a t i o n
DQ6: Toggle Bit I ................................................................................................83
Figure 7. Toggle Bit Algorithm.............................................. 84
CosmoRAM
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Pin Description (32M) . . . . . . . . . . . . . . . . . . . . . . .117
Functional Description . . . . . . . . . . . . . . . . . . . . . 118
Asynchronous Operation (Page Mode) .......................................................118
DQ2: Toggle Bit II .............................................................................................. 84
Table 19. DQ6 and DQ2 Indications ..................................... 85
Reading Toggle Bits DQ6/DQ2 ..................................................................... 85
DQ5: Exceeded Timing Limits ....................................................................... 86
DQ3: Sector Erase Timer ................................................................................ 86
Table 20. Write Operation Status ......................................... 87
Functional Description . . . . . . . . . . . . . . . . . . . . . 119
Synchronous Operation (Burst Mode) ........................................................119
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . .88
Figure 8. Maximum Negative Overshoot Waveform ................. 88
Figure 9. Maximum Positive Overshoot Waveform .................. 88
State Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Initial/Standby State ...........................................................................................120
Figure 38. Initial Standby State Diagram ............................ 120
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 89
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .90
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 10. Test Setup ......................................................... 91
Table 21. Test Specifications ............................................... 91
Asynchronous Operation State ....................................................................120
Figure 39. Asynchronous Operation State Diagram............... 120
Synchronous Operation State ........................................................................121
Figure 40. Synchronous Operation Diagram ........................ 121
Key to Switching Waveforms . . . . . . . . . . . . . . . 91
Switching Waveforms . . . . . . . . . . . . . . . . . . . . . 91
Figure 11. Input Waveforms and Measurement Levels............. 91
Functional Description . . . . . . . . . . . . . . . . . . . . . 121
Power-up ...............................................................................................................121
Configuration Register ......................................................................................121
CR Set Sequence ................................................................................................121
Power Down .......................................................................................................124
Burst Read/Write Operation .........................................................................124
Figure 41. Burst Read Operation........................................ 125
Figure 42. Burst Write Operation ....................................... 125
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .92
V
CC
Power-up ..................................................................................................... 92
CLK Characterization ....................................................................................... 92
Figure 12. V
CC
Power-up Diagram ........................................ 92
Figure 13. CLK Characterization ........................................... 92
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 93
Synchronous/Burst Read @ V
IO
= 1.8 V ......................................................93
Figure 14. CLK Synchronous Burst Mode Read
(rising active CLK).............................................................. 94
Figure 15. CLK Synchronous Burst Mode Read
(Falling Active Clock) .......................................................... 94
Figure 16. Synchronous Burst Mode Read.............................. 95
Figure 17. 8-word Linear Burst with Wrap Around................... 95
Figure 18. Linear Burst with RDY Set One Cycle Before Data .... 96
Figure 19. Asynchronous Mode Read with Latched Addresses... 98
Figure 20. Asynchronous Mode Read..................................... 98
Figure 21. Reset Timings..................................................... 99
Figure 22. Asynchronous Program Operation Timings: AVD#
Latched Addresses ........................................................... 101
Figure 23. Asynchronous Program Operation Timings: WE#
Latched Addresses ........................................................... 102
Figure 24. Synchronous Program Operation Timings: WE# Latched
Addresses ....................................................................... 103
Figure 25. Synchronous Program Operation Timings: CLK Latched
Addresses ....................................................................... 104
Figure 26. Chip/Sector Erase Command Sequence................ 105
Figure 27. Accelerated Unlock Bypass Programming Timing ... 106
Figure 28. Data# Polling Timings
(During Embedded Algorithm)............................................ 107
Figure 29. Toggle Bit Timings (During Embedded Algorithm).. 107
Figure 30. Synchronous Data Polling
Timings/Toggle Bit Timings................................................ 108
Figure 31. DQ2 vs. DQ6 .................................................... 108
Figure 32. Temporary Sector Unprotect Timing Diagram........ 109
Figure 33. Sector/Sector Block Protect and Unprotect Timing
Diagram.......................................................................... 110
Figure 34. Latency with Boundary Crossing.......................... 111
Figure 35. Latency with Boundary Crossing into Program/Erase
Bank .............................................................................. 112
Figure 36. Example of Wait States Insertion ........................ 113
Figure 37. Back-to-Back Read/Write Cycle Timings ............... 114
CLK Input Function ..........................................................................................125
ADV# Input Function .......................................................................................126
WAIT# Output Function ................................................................................126
Figure 43. Read Latency Diagram ...................................... 127
Address Latch by ADV# .................................................................................128
Burst Length ........................................................................................................128
Single Write .........................................................................................................128
Write Control ....................................................................................................129
Figure 44. Write Controls.................................................. 129
Asynchronous Mode Read @ V
IO
= 1.8 V ..................................................97
Burst Read Suspend ..........................................................................................129
Figure 45. Burst Read Suspend Diagram............................. 130
Burst Write Suspend ........................................................................................130
Figure 46. Burst Write Suspend Diagram ............................ 130
Erase/Program Operations @ V
IO
= 1.8 V ................................................100
Burst Read Termination ..................................................................................130
Figure 47. Burst Read Termination Diagram ........................ 131
Burst Write Termination ................................................................................. 131
Figure 48. Burst Write Termination Diagram........................ 131
Absolute Maximum Ratings . . . . . . . . . . . . . . . .
Recommended Operating Conditions (See
Warning Below) . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Pin Capacitance . . . . . . . . . . . . . . . . . . .
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . .
132
132
132
133
134
Temporary Sector Unprotect .......................................................................109
Read Operation .................................................................................................134
Write Operation ...............................................................................................136
Synchronous Operation - Clock Input (Burst Mode) ............................ 137
Synchronous Operation - Address Latch (Burst Mode) ....................... 137
Synchronous Read Operation (Burst Mode) ............................................138
Synchronous Write Operation (Burst Mode) ..........................................139
Power Down Parameters ...............................................................................140
Other Timing Parameters ...............................................................................140
AC Test Conditions .........................................................................................140
AC Measurement Output Load Circuit ......................................................141
Figure 49. Output Load Circuit........................................... 141
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 50. Asynchronous Read Timing #1-1 (Basic Timing) ... 142
Figure 51. Asynchronous Read Timing #1-2 (Basic Timing) ... 142
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S71WS256/128/064J_CSA0 October 27, 2004
A d v a n c e
I n f o r m a t i o n
Figure 52. Asynchronous Read Timing #2
(OE# & Address Access) ................................................... 143
Figure 53. Asynchronous Read Timing #3
(LB# / UB# Byte Access) .................................................. 143
Figure 54. Asynchronous Read Timing #4 (Page Address Access
after CE1# Control Access)................................................ 144
Figure 55. Asynchronous Read Timing #5 (Random and Page
Address Access)............................................................... 144
Figure 56. Asynchronous Write Timing #1-1 (Basic Timing) ... 145
Figure 57. Asynchronous Write Timing #1-2 (Basic Timing) ... 145
Figure 58. Asynchronous Write Timing #2 (WE# Control) ...... 146
Figure 59. Asynchronous Write Timing #3-1 (WE# / LB# / UB#
Byte Write Control) .......................................................... 146
Figure 60. Asynchronous Write Timing #3-2 (WE# / LB# / UB#
Byte Write Control) .......................................................... 147
Figure 61. Asynchronous Write Timing #3-3 (WE# / LB# / UB#
Byte Write Control) .......................................................... 147
Figure 62. Asynchronous Write Timing #3-4 (WE# / LB# / UB#
Byte Write Control) .......................................................... 148
Figure 63. Asynchronous Read / Write Timing #1-1
(CE1# Control) ................................................................ 148
Figure 64. Asynchronous Read / Write Timing #1-2 (CE1# / WE# /
OE# Control)................................................................... 149
Figure 65. Asynchronous Read / Write Timing #2 (OE#, WE#
Control) .......................................................................... 149
Figure 66. Asynchronous Read / Write Timing #3 (OE,# WE#, LB#,
UB# Control)................................................................... 150
Figure 67. Clock Input Timing ............................................ 150
Figure 68. Address Latch Timing (Synchronous Mode)........... 151
Figure 69. 32M Synchronous Read Timing #1 (OE# Control).. 152
Figure 70. 32M Synchronous Read Timing #2 (CE1# Control) 153
Figure 71. 32M Synchronous Read Timing #3 (ADV# Control) 154
Figure 72. Synchronous Read - WAIT# Output Timing (Continuous
Read)............................................................................. 155
Figure 73. 64M Synchronous Read Timing #1 (OE# Control) . 156
Figure 74. 64M Synchronous Read Timing #2 (CE1# Control) 157
Figure 75. 64M Synchronous Read Timing #3 (ADV# Control) 158
Figure 76. Synchronous Write Timing #1 (WE# Level Control) 159
Figure 77. Synchronous Write Timing #2 (WE# Single Clock Pulse
Control) ......................................................................... 160
Figure 78. Synchronous Write Timing #3 (ADV# Control) ..... 161
Figure 79. Synchronous Write Timing #4 (WE# Level Control,
Single Write)................................................................... 162
Figure 80. 32M Synchronous Read to Write Timing #1(CE1#
Control) ......................................................................... 163
Figure 81. 32M Synchronous Read to Write Timing #2(ADV#
Control) ......................................................................... 164
Figure 82. 64M Synchronous Read to Write Timing #1(CE1#
Control) ......................................................................... 165
Figure 83. 64M Synchronous Read to Write Timing #2(ADV#
Control) ......................................................................... 166
Figure 84. Synchronous Write to Read Timing #1
(CE1# Control) ............................................................... 167
Figure 85. Synchronous Write to Read Timing #2
(ADV# Control) ............................................................... 168
Figure 86. Power-up Timing #1 ......................................... 169
Figure 87. Power-up Timing #2 ........................................ 169
Figure 88. Power Down Entry and Exit Timing ..................... 169
Figure 89. Standby Entry Timing after Read or Write............ 170
Figure 90. Configuration Register Set Timing #1 (Asynchronous
Operation)...................................................................... 170
Figure 91. Configuration Register Set Timing #2 (Synchronous
Operation)...................................................................... 171
Revision Summary
October 27, 2004 S71WS256/128/064J_CSA0
5
Special Edition for Assessment Centres
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