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PRELIMINARY TECHNICAL DATA
a
Preliminary Technical Data
FEATURES
Specified for V
DD
of 1.6 V to 3.6 V
Low Power:
0.62 typ mW at 100 kSPS with 3V Supplies
0.48 typ mW at 50 kSPS with 3.6 V Supplies
0.12 typ mW at 100 kSPS with 1.6V Supplies
Fast Throughput Rate: 200KSPS
Wide Input Bandwidth:
71dB SNR at 30 kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High Speed Serial Interface
SPI/QSPI/mWire/DSP Compatible
Automatic Power Down
Standby Mode: 0.5
µ
A max
6-Lead SOT-23 Package
8-Lead MSOP Package
APPLICATIONS
Battery Powered Systems
Medical Instruments
Remote Data Acquisition
Isolated Data Acquisition
GENERAL DESCRIPTION
1.6 V, Micro-Power,
8/10/12-Bit ADCs in 6 Lead SOT-23
AD7466/AD7467/AD7468
FUNCTIONAL BLOCK DIAGRAM
VDD
VIN
T/H
12 /10 /8-BIT
SUCCESSIVE
APPROXIMATION
ADC
SCLK
CONTROL LOGIC
SDATA
CS
AD7466/67/68
GND
PRODUCT HIGHLIGHTS
The AD7466/AD7467/AD7468 are 12-/10-/8-bit, high
speed, low power, successive-approximation ADCs
respectively. The parts operate from a single 1.6V to 3.6V
power supply and feature throughput rates up to 200kSPS.
The parts contain a low-noise, wide bandwidth track/hold
amplifier which can handle input frequencies in excess of
TBDkHz.
The conversion process and data acquisition are controlled
using
CS
and the serial clock, allowing the devices to
interface with microprocessors or DSPs. The input signal
is sampled on the falling edge of
CS
and the conversion is
also initiated at this point. There are no pipelined delays
associated with the part.
The AD7466/AD7467/AD7468 use advanced design tech-
niques to achieve very low power dissipation at high
throughput rates.
The reference for the part is taken internally from V
DD.
This allows the widest dynamic input range to the ADC.
Thus the analog input range for the part is 0 to V
DD
. The
conversion rate is determined by the SCLK.
1. Specified for Supply voltages of 1.6V to 3.6V.
2. 8-/10-/12-Bit ADCs in a SOT-23 package.
3. High Throughput rate with Low Power Consumption.
4. Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock
allowing the conversion time to be reduced through the
serial clock speed increase. Automatic Power down after
conversion, which allows the average power consumption
to be reduced when in power down. Current consump-
tion is 0.5µA max when in power down.
5. Reference derived from the power supply.
6. No Pipeline Delay.
The part features a standard successive-approximation
ADC with accurate control of the conversions via a
CS
input.
REV. PrF
11/02
One Technology Way, P Box 9106, Norwood, MA 02062-9106, U.S.A.
.O.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2002
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
PRELIMINARY TECHNICAL DATA
AD7466–SPECIFICATIONS
Parameter
DYNAMIC PERFORMANCE
Signal-to-Noise + Distortion (SINAD)
2
Signal-to-Noise Ratio (SNR)
2
Total Harmonic Distortion (THD)
2
Peak Harmonic or Spurious Noise (SFDR)
2
Intermodulation Distortion (IMD)
2
Second Order Terms
Third Order Terms
Aperture Delay
Aperture Jitter
Full Power Bandwidth
Full Power Bandwidth
DC ACCURACY
Resolution
Integral Nonlinearity
2
Differential Nonlinearity
2
Offset Error
3
Gain Error
3
Total Unadjusted Error (TUE)
3
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
, SCLK Pin
Input Current, I
IN
,
CS
Pin
Input Capacitance, C
IN3
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
3
Output Coding
CONVERSION RATE
Conversion Time
Throughput Rate
POWER REQUIREMENTS
V
DD
I
DD
Normal Mode (Static)
Normal Mode (Operational)
4
1
(V
DD
= 1.6 V to 3.6 V, f
SCLK
= 3.4 MHz, f
SAMPLE
= 100 kSPS unless otherwise noted;
T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
B Version
1, 2
70
71
–78
–80
–78
–78
10
30
TBD
TBD
12
±1.5
±0.6
–0.9/+1.5
±0.75
±1.5
±1.5
TBD
0 to V
DD
±1
30
0.7(V
DD
)
2
0.2(V
DD
)
0.3(V
DD
)
0.8
±1
±1
10
Unit
dB
dB
dB
dB
min
min
typ
typ
Test Conditions/Comments
f
IN
= 30 kHz Sine Wave
fa = 29.1 kHz, fb = 29.9 kHz
dB typ
dB typ
ns typ
ps typ
MHz typ
MHz typ
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
@ 3 dB
@ 0.1 dB
max
typ
max Guaranteed No Missed Codes to 12 Bits
typ
max
max
max
V
µA max
pF typ
V min
V min
V max
V max
V max
µA max
µA typ
pF max
1.6V Vdd< 2.7V
2.7V Vdd 3.6V
1.6V Vdd< 1.8V
1.8V Vdd< 2.7V
2.7V Vdd 3.6V
Typically 10 nA, V
IN
= 0 V or V
DD
V
DD
– 0.2
V min
0.2
V max
±10
µA max
10
pF max
Straight (Natural) Binary
4.70
200
1.6/3.6
TBD
TBD
220
110
20
165
80
16
100
50
10
µs max
kSPS max
V min/max
µA
typ
µA
typ
µA
max
µA
typ
µA
typ
µA
max
µA
typ
µA
typ
µA
max
µA
typ
µA
typ
I
SOURCE
= 200 µA; V
DD
= 1.6 V to 3.6 V
I
SINK
= 200 µA
16 SCLK Cycles
See Serial Interface Section
Digital I/Ps = 0 V or V
DD
V
DD
= 2.7V to 3.6V, SCLK On or Off
V
DD
= 1.6V to 2.5V, SCLK On or Off
V
DD
= 3 V, f
SAMPLE
= 100 KSPS
V
DD
= 3 V, f
SAMPLE
= 50 KSPS
V
DD
= 3 V, f
SAMPLE
= 10 KSPS
V
DD
= 2.5 V, f
SAMPLE
= 100 KSPS
V
DD
= 2.5 V, f
SAMPLE
= 50 KSPS
V
DD
= 2.5 V, f
SAMPLE
= 10 KSPS
V
DD
= 1.8 V, f
SAMPLE
= 100 KSPS
V
DD
= 1.8 V, f
SAMPLE
= 50 KSPS
V
DD
= 1.8 V, f
SAMPLE
= 10 KSPS
–2–
REV. PrF
PRELIMINARY TECHNICAL DATA
AD7466–SPECIFICATIONS
Parameter
1
(V
DD
= 1.6 V to 3.6 V, f
SCLK
= 3.4 MHz, f
SAMPLE
= 100 kSPS unless otherwise noted;
T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
B Version
1, 2
Unit
Test Conditions/Comments
POWER REQUIREMENTS(continued)
Power-Down
Power Dissipation
5
Normal Mode (Operational)
0.5
TBD
µA max
µA max
SCLK Off
SCLK On
Power-Down
0.66
0.42
0.18
TBD
TBD
TBD
mW max
mW max
mW max
µW max
µW max
µW max
V
DD
=
V
DD
=
V
DD
=
V
DD
=
V
DD
=
V
DD
=
3V, f
SAMPLE
=100KSPS
2.5V, f
SAMPLE
=100KSPS
1.8V, f
SAMPLE
=100KSPS
3V, SCLK Off
2.5V, SCLK Off
1.8V, SCLK Off
NOTES
1
Temperature ranges as follows: B Versions: –40°C to +85°C.
2
See Terminology.
3
Sample tested at 25°C to ensure compliance.
4
See TPC10 Supply current vs Supply voltage.
5
See Power Consumption section.
Specifications subject to change without notice.
AD7467–SPECIFICATIONS
Parameter
DYNAMIC PERFORMANCE
Signal-to-Noise + Distortion (SINAD)
2
Total Harmonic Distortion (THD)
2
Peak Harmonic or Spurious Noise (SFDR)
2
Intermodulation Distortion (IMD)
2
Second Order Terms
Third Order Terms
Aperture Delay
Aperture Jitter
Full Power Bandwidth
Full Power Bandwidth
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
Total Unajusted Error (TUE)
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
, SCLK Pin
Input Current, I
IN
,
CS
Pin
Input Capacitance, C
IN3
1
(V
DD
= 1.6 V to 3.6 V, f
SCLK
= 3.4 MHz, f
SAMPLE
= 100 kSPS unless otherwise noted;
T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
B Version
1, 2
61
–73
–74
–78
–78
10
30
TBD
TBD
10
±1
±0.9
±1
±1
TBD
0 to V
DD
±1
30
0.7(V
DD
)
2
0.2(V
DD
)
0.3(V
DD
)
0.8
±1
±1
10
–3–
Unit
dB min
dB max
dB max
fa = 29.1 kHz, fb = 29.9 kHz
dB typ
dB typ
ns typ
ps typ
MHz typ
MHz typ
Bits
LSB
LSB
LSB
LSB
LSB
Test Conditions/Comments
f
IN
= 30 kHz Sine Wave,
@ 3 dB
@ 0.1 dB
max
max
max
max
max
Guaranteed No Missed Codes to 10 Bits
V
µA max
pF typ
V min
V min
V max
V max
V max
µA max
µA typ
pF max
1.6V Vdd< 2.7V
2.7V Vdd 3.6V
1.6V Vdd< 1.8V
1.8V Vdd< 2.7V
2.7V Vdd 3.6V
Typically 10 nA, V
IN
= 0 V or V
DD
REV. PrF
PRELIMINARY TECHNICAL DATA
AD7467–SPECIFICATIONS
Parameter
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
3
Output Coding
CONVERSION RATE
Conversion Time
Throughput Rate
POWER REQUIREMENTS
V
DD
I
DD
Normal Mode (Static)
Normal Mode (Operational)
1
(V
DD
= 1.6 V to 3.6 V, f
SCLK
= 3.4 MHz, f
SAMPLE
= 100 kSPS unless otherwise noted;
T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
B Version
1, 2
Unit
Test Conditions/Comments
I
SOURCE
= 200 µA;
I
SINK
= 200 µA
V
DD
– 0.2
V min
0.2
V max
±10
µA max
10
pF max
Straight (Natural) Binary
3.52
275
1.6/3.6
TBD
TBD
200
150
90
0.5
TBD
0.6
0.38
0.17
TBD
TBD
TBD
12 SCLK Cycles with SCLK at 3.4 MHz
µs
max
kSPS max See Serial Interface Section
V min/max
µA
typ
µA
typ
µA
max
µA
max
µA
max
µA max
µA max
mW max
mW max
mW max
µW max
µW max
µW max
Digital I/Ps = 0 V or V
DD
V
DD
= 2.7V to 3.6V, SCLK On or Off
V
DD
= 1.6V to 2.5V, SCLK On or Off
V
DD
= 3V, f
SAMPLE
=100 KSPS
V
DD
= 2.5V, f
SAMPLE
=100 KSPS
V
DD
= 1.8V, f
SAMPLE
=100 KSPS
SCLK Off
SCLK On
V
DD
=
V
DD
=
V
DD
=
V
DD
=
V
DD
=
V
DD
=
3V, f
SAMPLE
=100KSPS
2.5V, f
SAMPLE
=100KSPS
1.8V, f
SAMPLE
=100KSPS
3V, SCLK Off
2.5V, SCLK Off
1.8V, SCLK Off
Power-Down
Power Dissipation
4
Normal Mode (Operational)
Power-Down
NOTES
1
Temperature ranges as follows: B Versions: –40°C to +85°C.
2
See Terminology.
3
Sample tested at 25°C to ensure compliance.
4
See Power Consumption section.
Specifications subject to change without notice.
AD7468–SPECIFICATIONS
Parameter
DYNAMIC PERFORMANCE
Signal-to-Noise + Distortion (SINAD)
2
Total Harmonic Distortion (THD)
2
Peak Harmonic or Spurious Noise (SFDR)
2
Intermodulation Distortion (IMD)
2
Second Order Terms
Third Order Terms
Aperture Delay
Aperture Jitter
Full Power Bandwidth
Full Power Bandwidth
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
Total Unadjusted Error (TUE)
1
(V
DD
= 1.6 V to 3.6 V, f
SCLK
= 3.4 MHz, f
SAMPLE
= 100 kSPS unless otherwise noted;
T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
B Version
1, 2
Unit
49
–65
–65
–68
–68
10
30
TBD
TBD
8
±0.5
±0.5
±0.5
±0.5
±0.5
dB min
dB max
dB max
fa = 29.1 kHz, fb = 29.9 kHz
dB typ
dB typ
ns typ
ps typ
MHz typ
MHz typ
Bits
LSB
LSB
LSB
LSB
LSB
Test Conditions/Comments
f
IN
=30 kHz Sine Wave
@ 3 dB
@ 0.1 dB
max
max
max
max
max
Guaranteed No Missed Codes to 8 Bits
–4–
REV. PrF
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