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WSF512K32-29H2IA

Description
Memory Circuit, 512KX32, CMOS, CPGA66, 1.385 X 1.385 INCH, HERMETIC SEALED, CERAMIC, PGA-66
Categorystorage    storage   
ManufacturerMicrosemi
Websitehttps://www.microsemi.com
Download Datasheet Parametric View All

WSF512K32-29H2IA Overview

Memory Circuit, 512KX32, CMOS, CPGA66, 1.385 X 1.385 INCH, HERMETIC SEALED, CERAMIC, PGA-66

WSF512K32-29H2IA Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Parts packaging codePGA
package instruction1.385 X 1.385 INCH, HERMETIC SEALED, CERAMIC, PGA-66
Contacts66
Reach Compliance Codeunknown
Other featuresSRAM IS ORGANISED AS 512K X 32
JESD-30 codeS-CPGA-P66
JESD-609 codee0
length35.2 mm
memory density16777216 bit
Memory IC TypeMEMORY CIRCUIT
memory width32
Number of functions1
Number of terminals66
word count524288 words
character code512000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize512KX32
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codePGA
Package shapeSQUARE
Package formGRID ARRAY
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum seat height5.7 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTIN LEAD
Terminal formPIN/PEG
Terminal pitch2.54 mm
Terminal locationPERPENDICULAR
Maximum time at peak reflow temperatureNOT SPECIFIED
width35.2 mm
Base Number Matches1
WSF512K32-XXX
512K
X
32 SRAM / NOR FLASH MODULE
FEATURES

Access Times of 25ns (SRAM) and 70, 90ns (FLASH)

Packaging
• 66 pin, PGA Type, 1.385" square HIP, Hermetic Ceramic
HIP (Package 402)
• 68 lead, Hermetic CQFP (G2T), 22.4mm (0.880") square
(Package 509) 4.57mm (0.180") height. Designed to
fit JEDEC 68 lead 0.990" CQFJ footprint (Figure 2).
Package to be developed.

512Kx32 5V SRAM

512Kx32 5V NOR Flash

Organized as 512Kx32 of SRAM and 512Kx32 of Flash
Memory with common Data Bus

Low Power CMOS

Commercial, Industrial and Military Temperature Ranges

TTL Compatible Inputs and Outputs

Built in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation

Weight - 13 grams typical
FLASH MEMORY FEATURES

100,000 Erase/Program Cycles Minimum

Sector Architecture
• 8 equal size sectors of 64KBytes each
• Any combination of sectors can be concurrently erased.
Also supports full chip erase

5 Volt Programming

Embedded Erase and Program Algorithms

Hardware Write Protection

Page Program Operation and Internal Program Control
Time.
* This product is subject to change without notice.
For Flash programming information and waveforms refer to Flash programming 4M5 Application Note
AN0037
Figure 1 – PIN CONFIGURATION FOR
WSF512K32-29H2X
I/O0-31
PIN DESCRIPTION
Data Inputs/Outputs
Address Inputs
SRAM Write Enable
SRAM Chip Select
Output Enable
Power Supply
Ground
Not Connected
Flash Write Enable
Flash Chip Select
A0-18
SWE1-4#
SCS#
OE#
VCC
GND
NC
FWE1-4#
FCS#
TOP VIEW
1
I/O8
I/O9
I/O10
A14
A16
A11
A0
A18
I/O0
I/O1
I/O2
11
22
12
FWE2#
SWE2#
GND
I/O11
A10
A9
A15
VCC
FCS#
SCS#
I/O3
33
23
I/O15
I/O14
I/O13
I/O12
OE#
A17
FWE1#
I/O7
I/O6
I/O5
I/O4
I/O24
I/O25
I/O26
A7
A12
SWE1#
A13
A8
I/O16
I/O17
I/O18
44
34
VCC
SWE4#
FWE4#
I/O27
A4
A5
A6
FWE3#
SWE3#
GND
I/O19
55
45
I/O31
I/O30
I/O29
I/O28
A1
A2
A3
I/O23
I/O22
I/O21
I/O20
66
56
BLOCK DIAGRAM
FWE
1
# SWE
1
#
OE#
A0-18
SCS#
FCS#
512K x 8 Flash
512K x 8 SRAM
512K x 8 Flash
512K x 8 SRAM
512K x 8 Flash
512K x 8 SRAM
512K x 8 Flash
512K x 8 SRAM
FWE
2
# SWE
2
#
FWE
3
# SWE
3
#
FWE
4
# SWE
4
#
I/O0-7
I/O8-15
I/O16-23
I/O24-31
Microsemi Corporation reserves the right to change products or specifications without notice.
May 2012
Rev. 11
© 2012 Microsemi Corporation. All rights reserved.
1
Microsemi Corporation • (602) 437-1520 • www.microsemi.com
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