7A
CY2277A
Pentium
®
/II, 6x86, K6 Clock Synthesizer/Driver for Desktop/
Mobile PCs with Intel
®
82430TX and 2 DIMMs or 3 SO-DIMMs
Features
• Mixed 2.5V and 3.3V operation
• Complete clock solution to meet requirements of Pen-
tium
®
, Pentium
®
II, 6x86, or K6 motherboards
— Four CPU clocks at 2.5V or 3.3V
— Up to eight 3.3V SDRAM clocks
— Seven 3.3V synchronous PCI clocks, one free
running
— Two 3.3V USB/IO clocks at 48 or 24 MHz, selectable
by serial interface
— One 2.5V IOAPIC clock at 14.318 MHz
— Two 3.3V Ref. clocks at 14.318 MHz
• Factory-EPROM programmable CPU, PCI, and USB/IO
clock frequencies for custom configuration
• Factory-EPROM programmable output drive and slew
rate for EMI customization
• MODE Enable pin for CPU_STOP and PCI_STOP
• SMBus serial configuration interface
• Available in space-saving 48-pin SSOP and TSSOP
packages.
The CY2277A has power-down, CPU stop and PCI stop pins
for power management control. The CPU stop and PCI stop
are controlled by the MODE pin. They are multiplexed with
SDRAM clock outputs, and are selected when the MODE pin
is driven LOW. Additionally, these inputs are synchronized
on-chip, enabling glitch-free transitions. When the
CPU_STOP input is asserted, the CPU outputs are driven
LOW. When the PCI_STOP input is asserted, the PCI outputs
(except the free-running PCI clock) are driven LOW. Finally,
when the PWR_DWN pin is asserted, the reference oscillator
and PLLs are shut down, and all outputs are driven LOW.
The CY2277A outputs are designed for low EMI emission.
Controlled rise and fall times, unique output driver circuits and
factory-EPROM programmable output drive and slew-rate en-
able optimal configurations for EMI control.
CY2277A Selector Guide
Clock Outputs
CPU (60, 66.6 MHz)
CPU (33.3, 66.6 MHz)
CPU (SMBus select-
able)
PCI (CPU/2)
SDRAM
USB/IO (48 or 24 MHz)
IOAPIC (14.318 MHz)
Ref (14.318 MHz)
CPU-PCI delay
Note:
1. One free-running PCI clock.
-1/-1M
4
--
--
7
[1]
6/8
2
1
2
-3
--
4
--
7
[1]
6/8
2
1
2
-7M
4
--
--
7
[1]
6/8
2
1
2
<1 ns
-12/
-12M/
-12I
4
--
--
7
[1]
6/8
2
1
2
1–4 ns
Functional Description
The CY2277A is a Clock Synthesizer/Driver for Pentium, Pen-
tium II, 6X86, and K6 portable PCs designed with the Intel
®
82430TX or similar chipsets. There are three available options
as shown in the selector guide
The CY2277A outputs four CPU clocks at 2.5V or 3.3V with up
to nine selectable frequencies. There are up to eight 3.3V
SDRAM clocks and seven PCI clocks, running at one half the
CPU clock frequency. One of the PCI clocks is free-running.
Additionally, the part outputs two 3.3V USB/IO clocks at 48
MHz or 24 MHz, one 2.5V IOAPIC clock at 14.318 MHz, and
two 3.3V reference clocks at 14.318 MHz. The CPU, PCI,
USB, and IO clock frequencies are factory-EPROM program-
mable for easy customization with fast turnaround times.
1–6 ns 1–6 ns
Logic Block Diagram
IOAPIC (14.318 MHz)
V
DDQ2
REF [0–1]
(14.318)
Pin Configuration
SSOP
Top View
REF1
REF0
V
SS
XTALIN
CPUCLK[0–3]
XTALOUT
MODE
V
DDQ3
V
DDCPU
PCICLK_F
PCICLK0
SDRAM[0–5]
V
SS
PCICLK1
SDRAM6/CPU_STOP
PCICLK2
PCICLK3
PCICLK4
SDRAM7/PCI_STOP
V
DDQ3
PCICLK5
V
SS
SEL
PCI[0–5]
SDATA
SCLK
PCICLK_F
V
DDQ3
USBCLK/IOCLK[0:1]
USBCLK/IOCLK
USBCLK/IOCLK
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
AV
DD
PWR_SEL
V
DDQ2
IOAPIC
PWR_DWN
V
SS
CPUCLK0
CPUCLK1
V
DDCPU
CPUCLK2
CPUCLK3
V
SS
SDRAM0
SDRAM1
V
DDQ3
SDRAM2
SDRAM3
V
SS
SDRAM4
SDRAM5
V
DDQ3
SDRAM6/CPU_STOP
SDRAM7/PCI_STOP
AV
DD
XTALIN
XTALOUT
CPU
PLL
STOP
LOGIC
SEL
MODE
EPROM
SYS
PLL
/2
Delay
STOP
LOGIC
SERIAL
INTERFACE
CONTROL
LOGIC
Divide and
Mux Logic
PWR_DWN
SCLK
SDATA
Cypress Semiconductor Corporation
Document #: 38-07332 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised November 15, 2001
CY2277A-1,-1M,-3,-7M,-12,-12M,-12I
14.318
MHz
OSC.
CY2277A
Pin Summary
Name
V
DDQ3
V
DDQ2
V
DDCPU
AV
DD
V
SS
XTALIN
[2]
XTALOUT
[2]
MODE
SEL
SDATA
SCLK
PWR_DWN
PWR_SEL
SDRAM7/PCI_STOP
SDRAM6/CPU_STOP
SDRAM[0:5]
CPUCLK[0:3]
PCICLK[0:5]
PCICLK_F
IOAPIC
REF[0:1]
USBCLK/IOCLK
Pins
7, 15, 21, 28, 34
46
40
25, 48
4
5
6
18
19
20
44
47
26
27
36, 35, 33, 32, 30, 29
42, 41, 39, 38
9, 11, 12, 13, 14, 16
8
45
1, 2
22, 23
Description
3.3V Digital voltage supply
IOAPIC Digital voltage supply, 2.5V
CPU Digital voltage supply, 2.5V or 3.3V
3.3V Analog voltage supply
Reference crystal input
Reference crystal feedback
Mode select input, enables power management features
Select input to enable 66.66 MHz or 60 MHz CPU clock (See Function
tables.)
SMBus serial data input for serial configuration port
SMBus serial clock input for serial configuration port
Active low control input to put osc., PLLs, and outputs in power down state
Power select input, indicates whether V
DDCPU
is at 2.5V or 3.3V
HIGH = 3.3V, LOW=2.5V (internal pull-up to V
DD
)
SDRAM clock output. Also, active LOW control input to stop PCI clocks,
enabled when MODE is LOW
SDRAM clock output. Also, active LOW control input to stop CPU clocks,
enabled when MODE is LOW
SDRAM clock outputs, have same frequency as CPU clocks
CPU clock outputs
PCI clock outputs
PCI clock output, free-running
IOAPIC clock output
Reference clock outputs, 14.318 MHz. REF0 drives 45 pF load
USB or IO clock outputs, frequency selected by serial word
3, 10, 17, 24, 31, 37, 43 Ground
Note:
2. For best accuracy, use a parallel-resonant crystal, C
LOAD
= 18 pF.
Document #: 38-07332 Rev. **
Page 2 of 19
CY2277A
Function Table (-1, -1M, -7M, -12, -12M, -12I)
SEL
0
1
XTALIN
14.318 MHz
14.318 MHz
CPUCLK[0:3]
SDRAM[0:7]
60.0 MHz
66.67 MHz
PCICLK[0:5]
PCICLK_F
30.0 MHz
33.33 MHz
REF[0:1]
IOAPIC
14.318 MHz
14.318 MHz
USBCLK / IOCLK
[3]
48.0 MHz / 24.0 MHz
48.0 MHz / 24.0 MHz
Function Table (-3)
SEL
0
1
XTALIN
14.318 MHz
14.318 MHz
CPUCLK[0:3]
SDRAM[0:7]
33.33 MHz
66.67 MHz
PCICLK[0:5]
PCICLK_F
16.67 MHz
33.33 MHz
REF[0:1]
IOAPIC
14.318 MHz
14.318 MHz
USBCLK / IOCLK
[3]
48.0 MHz / 24.0 MHz
48.0 MHz / 24.0 MHz
Actual Clock Frequency Values (-1, -1M, -3, -7M,
-12, -12M, -12I)
Clock Output
CPUCLK,
SDRAM
CPUCLK,
SDRAM
USBCLK
[4]
IOCLK
Target
Frequency
(MHz)
66.67
60.0
48.0
24.0
Actual
Frequency
(MHz)
66.654
60.0
48.008
24.004
PPM
–195
0
167
167
CPU and PCI Clock Driver Strengths
• Matched impedances on both rising and falling edges on
the output drivers
• Output impedance: 25Ω (typical) measured at 1.5V
Notes:
3. On power-up, the default frequency on these outputs is 48 MHz.
4. Meets Intel USB clock requirements.
Document #: 38-07332 Rev. **
Page 3 of 19
CY2277A
Power Management Logic
CPU_STOP
X
0
0
1
1
PCI_STOP
X
0
1
0
1
PWR_DWN
0
1
1
1
1
CPUCLK
LOW
LOW
LOW
66/60 MHz
66/60 MHz
PCICLK
LOW
LOW
33/30 MHz
LOW
33/30 MHz
PCICLK_F
Stopped
Running
Running
Running
Running
Other Clocks
Stopped
Running
Running
Running
Running
Osc.
Off
Running
Running
Running
Running
PLLs
Off
Running
Running
Running
Running
Serial Configuration Map
• The Serial bits will be read by the clock driver in the following
order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
.
.
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
• Reserved and unused bits should be programmed to “0”.
• SMBus Address for the CY2277A is:
Byte 0: Functional and Frequency Select Clock
Register (1 = Enable, 0 = Disable)
Bit
Pin #
Description
(Reserved) drive to ‘0’
(Reserved) drive to ‘0’ on -1, -1M, -3, -7M, -12,
-12M, -12I
(Reserved) drive to ‘0’ on -1, -1M, -3, -7M, -12,
-12M, -12I
(Reserved) drive to ‘0’ on -1, -1M, -3, -7M, -12,
-12M, -12I
48/24 MHz (Frequency Select) 1 = 48 MHz
(default), 0 = 24 MHz
48/24 MHz (Frequency Select) 1 = 48 MHz
(default), 0 = 24 MHz
Bit 1
1
1
0
0
Bit 0
1 - Three-State (see table below)
0 - N/A
1 - Test Mode (see table below)
0 - Normal Operation
Bit 7 --
Bit 6 --
Bit 5 --
Bit 4 --
Bit 3 23
A6
1
A5
1
A4
0
A3
1
A2
0
A1
0
A0
1
R/W
----
Bit 2 22
Bit 1 --
Bit 0
Select Functions
Outputs
Functional Description
Three-State
Test Mode
Hi-Z
TCLK/2
[5]
CPU
PCI, PCI_F
Hi-Z
TCLK/4
SDRAM
Hi-Z
TCLK/2
Ref
Hi-Z
TCLK
IOAPIC
Hi-Z
TCLK
IOCLK
Hi-Z
TCLK/4
USBCLK
Hi-Z
TCLK/2
Note:
5. TCLK supplied on the XTALIN, PIN 4.
Document #: 38-07332 Rev. **
Page 4 of 19
CY2277A
Byte 1: CPU, 24/48 MHz Active/Inactive
Register (1 = Active, 0 = Inactive), Default = Active
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
23
22
--
N/A
38
39
41
42
Description
48/24 MHz (Active/Inactive)
48/24 MHz (Active/Inactive)
(Reserved) drive to ‘0’
Not Used, drive 0
CPUCLK3 (Active/Inactive)
CPUCLK2 (Active/Inactive)
CPUCLK1 (Active/Inactive)
CPUCLK0 (Active/Inactive)
Byte 2: PCI Active/Inactive
Register (1 = Active, 0 = Inactive), Default = Active
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
--
8
16
14
13
12
11
9
Pin #
Description
(Reserved) drive to ‘0’
PCICLK_F (Active/Inactive)
PCICLK5 (Active/Inactive)
PCICLK4 (Active/Inactive)
PCICLK3 (Active/Inactive)
PCICLK2 (Active/Inactive)
PCICLK1 (Active/Inactive)
PCICLK0 (Active/Inactive)
Byte 3: SDRAM Active/Inactive
Register (1 = Active, 0 = Inactive), Default = Active
Bit
Pin #
Description
SDRAM7 (Active/Inactive)
SDRAM6 (Active/Inactive)
SDRAM5 (Active/Inactive)
SDRAM4 (Active/Inactive)
SDRAM3 (Active/Inactive)
SDRAM2 (Active/Inactive)
SDRAM1 (Active/Inactive)
SDRAM0 (Active/Inactive)
Bit 7 26
Bit 6 27
Bit 5 29
Bit 4 30
Bit 3 32
Bit 2 33
Bit 1 35
Bit 0 36
Byte 4: SDRAM Active/Inactive
Register (1 = Active, 0 = Inactive), Default = Active
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Description
Not used, drive to ‘0’
Not used, drive to ‘0’
Not used, drive to ‘0’
Not used, drive to ‘0’
Not used, drive to ‘0’
Not used, drive to ‘0’
Not used, drive to ‘0’
Not used, drive to ‘0’
Byte 5: Peripheral Active/Inactive
Register (1 = Active, 0 = Inactive), Default = Active
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
--
--
--
45
--
--
1
2
Description
(Reserved) drive to ‘0’
(Reserved) drive to ‘0’
(Reserved) drive to ‘0’
IOAPIC (Active/Inactive)
(Reserved) drive to ‘0’
(Reserved) drive to ‘0’
REF1 (Active/Inactive)
REF0 (Active/Inactive)
Byte 6: Reserved, for future use
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Supply Voltage ..................................................–0.5 to +7.0V
Input Voltage ............................................ –0.5V to V
DD
+ 0.5
Storage Temperature (Non-Condensing).... –65°C to +150°C
Junction Temperature............................................... +150°C
Package Power Dissipation.............................................. 1W
Static Discharge Voltage ........................................... >2000V
(per MIL-STD-883, Method 3015, like V
DD
pins tied together)
Document #: 38-07332 Rev. **
Page 5 of 19
Microcontroller MCU
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