IBM04368CXLBC-27 datasheet, PDF

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IBM04368CXLBC-27: DescriptionStandard SRAM, 256KX36, 1.8ns, CMOS, PBGA153, BGA-153; Categorystorage storage; File Size312KB，24 Pages; ManufacturerIBM; Websitehttp://www.ibm.com

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IBM04368CXLBC-27 Overview

Standard SRAM, 256KX36, 1.8ns, CMOS, PBGA153, BGA-153

IBM04368CXLBC-27 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	BGA
package instruction	BGA, BGA153,9X17,50
Contacts	153
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Maximum access time	1.8 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	370 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B153
JESD-609 code	e0
length	22 mm
memory density	9437184 bit
Memory IC Type	STANDARD SRAM
memory width	36
Number of functions	1
Number of terminals	153
word count	262144 words
character code	256000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature
organize	256KX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA153,9X17,50
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.5,2.5 V
Certification status	Not Qualified
Maximum seat height	2.679 mm
Maximum standby current	0.15 A
Minimum standby current	2.38 V
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm
Base Number Matches	1

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IBM04368CXLBC

IBM04188CXLBC

8Mb (256K x 36 & 512K x 18) SRAM

Features

• 256K x 36 or 512K x 18 organization

• CMOS technology

• Double-data-rate (DDR) and single-data-rate

(SDR) synchronous modes of operation

• Pipeline mode of operation

• Self-timed late write with full data coherency

• Single differential high-speed transceiver logic

(HSTL) clock with HSTL input and output levels

• 2.5V power supply, 1.5V V

DDQ

• Programmable impedance output driver

• Registered addresses, controls and data-ins

• Burst mode of operation

• Common I/O

• Asynchronous output enable

• Boundary scan using a limited set of JTAG

1149.1 functions

• 9 x 17 bump ball grid array package with SRAM

JEDEC standard pinout and boundary SCAN

order

Description

The IBM04368CXLBC and IBM04188CXLBC 8Mb

SRAMs are synchronous pipeline-mode, high-per-

formance CMOS static random-access memories

that have wide I/O and achieve 2ns cycle times. Sin-

gle differential CK clocks are used to initialize the

read/write operation, and all internal operations are

self-timed. At the rising edge of the CK clock,

addresses and controls are registered internally.

Data-outs are updated from output registers on the

next rising and falling edges of the CK clock, hence

the double data rate. Internal write buffers allow

write data to follow one cycle after addresses and

controls. The SRAM is operated with a single 2.5V

power supply and is compatible with HSTL I/O inter-

faces.

CXLBC_ds.fm.00

June 7, 2002

Page 1 of 24

IBM04368CXLBC

IBM04188CXLBC

8Mb (256K x 36 & 512K x 18) SRAM

SRAM Features

DDR and SDR Modes

Timing Diagram: Double-Data-Rate and Single-Data-Rate Modes

on page 6 shows input and output data

placements for both DDR and SDR modes. In DDR read mode, two sets of data-outs are generated from the

second rising and falling edges of the CK clock, assuming the first rising edge of the CK clock samples the

base address. The first of the two data-out sets (DOUT-A) is generated from the sampled base address

(Base-A). The second data-out set (DOUT-A’) is generated from the next burst order address, according to

the burst order definition. Similarly, a DDR write requires data-in placement on the second rising and falling

CK edges. In SDR read mode, only one set of data-outs is generated from the second rising CK edge. In SDR

write mode, one set of data-ins is sampled on the second rising CK edge. The user can switch from DDR to

SDR mode (or from SDR to DDR mode) during any LOAD (B1 = 0) operation.

Late Write

The late-write function allows write data to be registered one cycle after addresses and controls. This feature

eliminates one of two bus-turnaround cycles normally required when going from a read to a write operation.

Late write is accomplished by buffering write addresses and data. The SRAM array update occurs during the

third write cycle. Read-cycle addresses are monitored to determine if read data is to be supplied from the

SRAM array or the write buffer. Full data coherency is maintained for both DDR and SDR operations. As a

result, NOP (write buffer flush) operations are not required going from write cycles to read cycles.

Echo Clocks

Echo clocks CQ and CQ are generated from rising and falling edges of the CK clock, with access times repre-

sentative of the data-outs. Echo clocks keep running during write and NOP operations. Echo clock operation

is identical for both DDR and SDR operations. The close tracking of echo clocks and data-out timings allows

the echo clocks to be used as capture clocks for the data-outs by the receiving device.

CXLBC_ds.fm.00

June 7, 2002

Page 5 of 24

IBM04368CXLBC-27 Related Products

	IBM04368CXLBC-27	IBM04368CXLBC-25	IBM04368CXLBC-30
Description	Standard SRAM, 256KX36, 1.8ns, CMOS, PBGA153, BGA-153	Standard SRAM, 256KX36, 1.8ns, CMOS, PBGA153, BGA-153	Standard SRAM, 256KX36, 1.7ns, CMOS, PBGA153, BGA-153
Is it lead-free?	Contains lead	Contains lead	Contains lead
Is it Rohs certified?	incompatible	incompatible	incompatible
Parts packaging code	BGA	BGA	BGA
package instruction	BGA, BGA153,9X17,50	BGA, BGA153,9X17,50	BGA, BGA153,9X17,50
Contacts	153	153	153
Reach Compliance Code	unknown	unknown	unknown
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
Maximum access time	1.8 ns	1.8 ns	1.7 ns
Other features	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	370 MHz	400 MHz	333 MHz
I/O type	COMMON	COMMON	COMMON
JESD-30 code	R-PBGA-B153	R-PBGA-B153	R-PBGA-B153
JESD-609 code	e0	e0	e0
length	22 mm	22 mm	22 mm
memory density	9437184 bit	9437184 bit	9437184 bit
Memory IC Type	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM
memory width	36	36	36
Number of functions	1	1	1
Number of terminals	153	153	153
word count	262144 words	262144 words	262144 words
character code	256000	256000	256000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	85 °C	85 °C
organize	256KX36	256KX36	256KX36
Output characteristics	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	BGA	BGA
Encapsulate equivalent code	BGA153,9X17,50	BGA153,9X17,50	BGA153,9X17,50
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY	GRID ARRAY	GRID ARRAY
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
power supply	1.5,2.5 V	1.5,2.5 V	1.5,2.5 V
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	2.679 mm	2.679 mm	2.679 mm
Maximum standby current	0.15 A	0.15 A	0.15 A
Minimum standby current	2.38 V	2.38 V	2.38 V
Maximum supply voltage (Vsup)	2.625 V	2.625 V	2.625 V
Minimum supply voltage (Vsup)	2.375 V	2.375 V	2.375 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V	2.5 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	OTHER	OTHER	OTHER
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	BALL	BALL	BALL
Terminal pitch	1.27 mm	1.27 mm	1.27 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	14 mm	14 mm	14 mm
Maker	-	IBM	IBM
Maximum slew rate	-	0.75 mA	0.64 mA

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