March 2007
HYS72T64000HP–[25F/2.5/3/3S/3.7]–B
HYS72T128000HP–[25F/2.5/3/3S/3.7]–B
HYS72T128020HP–[25F/2.5/3/3S/3.7]–B
HYS72T256220HP–[25F/2.5/3/3S/3.7]–B
240-Pin Registered DDR2 SDRAM Modules
RDIMM SDRAM
DDR2 SDRAM
RoHS Compliant
Internet Data Sheet
Rev. 1.1
Internet Data Sheet
HYS72T[64/128/256]xxxHP–[25F/2.5/3/3S/3.7]–B
240-Pin Registered DDR2 SDRAM
HYS72T64000HP–[25F/2.5/3/3S/3.7]–B, HYS72T128000HP–[25F/2.5/3/3S/3.7]–B,
HYS72T128020HP–[25F/2.5/3/3S/3.7]–B, HYS72T256220HP–[25F/2.5/3/3S/3.7]–B
Revision History: 2007-03, Rev. 1.1
All
All
All
Adapted internet edition
Updated for HYS72T[64/128/256]×××–3.7–B Product Types
Qimonda update
Previous Revision: 2006-12, Rev. 1.01
Previous Revision: 2006-03, Rev. 1.0
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qag_techdoc_rev400 / 3.2 QAG / 2006-08-07
03292006-EO3M-LEK7
2
Internet Data Sheet
HYS72T[64/128/256]xxxHP–[25F/2.5/3/3S/3.7]–B
240-Pin Registered DDR2 SDRAM
1
Overview
This chapter gives an overview of the 1.8 V 240-Pin Registered DDR2 SDRAM Modules with parity bit product family and
describes its main characteristics.
1.1
Features
•
•
•
•
•
•
•
•
•
•
Programmable self refresh rate via EMRS2 setting
Programmable partial array refresh via EMRS2 settings
DCC enabling via EMRS2 setting
All inputs and outputs SSTL_18 compatible
Off-Chip Driver Impedance Adjustment (OCD) and On-Die
Termination (ODT)
Serial Presence Detect with E
2
PROM
RDIMM Dimensions (nominal): 30 mm high, 133.35 mm
wide
Based on standard reference card layouts Raw Card “F”,
“G“, “H“, ”J” and “L“
All speed grades faster than DDR2–400 comply with
DDR2–400 timing specifications.
RoHS compliant products
1)
• 240-Pin PC2–6400, PC2–5300 and PC2–4200 DDR2
SDRAM memory modules.
• One rank 64M
×72,
128M
×72,
and two ranks 128M
×72,
256M
×72
module organization, and 512M
×8,
512M
×4
chip organization
• Registered DIMM Parity bit for address and control bus
• 512 MB, 1 GB, and 2 GB module built with 512 Mbit DDR2
SDRAMs in P-TFBGA-60 chipsize packages.
• Standard Double-Data-Rate-Two Synchronous DRAMs
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power
supply
• Programmable CAS Latencies (3, 4, 5, 6), Burst Length
(4 & 8) and Burst Type
• Auto Refresh (CBR) and Self Refresh
TABLE 1
Performance Table
Product Type Speed Code
Speed Grade
Max. Clock Frequency
@CL6
@CL5
@CL4
@CL3
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
–2.5F
PC2–6400
5–5–5
–2.5
PC2–6400
6–6–6
400
333
266
200
15
15
45
60
–3
PC2–5300
4–4–4
—
333
333
200
12
12
45
57
–3S
PC2–5300
5–5–5
—
333
266
200
15
15
45
60
–3.7
PC2–4200
4–4–4
—
266
266
200
15
15
45
60
Unit
—
MHz
MHz
MHz
MHz
ns
ns
ns
ns
f
CK6
f
CK5
f
CK4
f
CK3
t
RCD
t
RP
t
RAS
t
RC
400
400
266
200
12.5
12.5
45
57.5
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.1, 2007-03
03292006-EO3M-LEK7
3
Internet Data Sheet
HYS72T[64/128/256]xxxHP–[25F/2.5/3/3S/3.7]–B
240-Pin Registered DDR2 SDRAM
1.2
Description
capacitive loading to the system bus, but adds one cycle to
the SDRAM timing. Decoupling capacitors are mounted on
the PCB board. The DIMMs feature serial presence detect
based on a serial E
2
PROM device using the 2-pin I
2
C
protocol. The first 128 bytes are programmed with
configuration data and the second 128 bytes are available to
the customer.
The Qimonda HYS72T[64/128/256]xxxHP–[25F/2.5/3/3S/3.7]–B
module family are Registered DIMM (with parity) modules
with 30 mm height based on DDR2 technology.
DIMMs are available as ECC modules in 64M
×
72 (512 MB),
128M
×
72 (1 GB), 256M x72 (2GB) organization and density,
intended for mounting into 240-Pin connector sockets.
The memory array is designed with 512-Mbit Double-Data-
Rate-Two (DDR2) Synchronous DRAMs. All control and
address signals are re-driven on the DIMM using register
devices and a PLL for the clock distribution. This reduces
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type
1)
PC2–6400
HYS72T64000HP–25F–B
HYS72T128000HP–25F–B
HYS72T128020HP–25F–B
HYS72T256220HP–25F–B
PC2–6400
HYS72T64000HP–2.5–B
HYS72T128000HP–2.5–B
HYS72T128020HP–2.5–B
HYS72T256220HP–2.5–B
PC2–5300
HYS72T64000HP–3–B
HYS72T128000HP–3–B
HYS72T128020HP–3–B
HYS72T256220HP–3–B
PC2–5300
HYS72T64000HP–3S–B
HYS72T128000HP–3S–B
HYS72T128020HP–3S–B
HYS72T256220HP–3S–B
PC2–4200
HYS72T64000HP–3.7–B
HYS72T128000HP–3.7–B
HYS72T128020HP–3.7–B
HYS72T256220HP–3.7–B
512 MB 1Rx8 PC2-4200P-444-12-F0
1 GB 1Rx4 PC2-4200P-444-12-H0
1 GB 2Rx8 PC2-4200P-444-12-G0
2 GB 2Rx4 PC2-4200P-444-12-J2
1 Rank ECC
1 Rank ECC
2 Ranks, ECC
2 Ranks, ECC
512 Mbit (×8)
512 Mbit (×4)
512 Mbit (×8)
512 Mbit (×4)
512 MB 1Rx8 PC2-5300P-555-12-F0
1 GB 1Rx4 PC2-5300P-555-12-H0
1 GB 2Rx8 PC2-5300P-555-12-G0
2 GB 2Rx4 PC2-5300P-555-12-J2
1 Rank ECC
1 Rank ECC
2 Ranks, ECC
2 Ranks, ECC
512 Mbit (×8)
512 Mbit (×4)
512 Mbit (×8)
512 Mbit (×4)
512 MB 1Rx8 PC2-5300P-444-12-F0
1 GB 1Rx4 PC2-5300P-444-12-H0
1 GB 2Rx8 PC2-5300P-444-12-G0
2 GB 2Rx4 PC2-5300P-444-12-J2
1 Rank ECC
1 Rank ECC
2 Ranks, ECC
2 Ranks, ECC
512 Mbit (×8)
512 Mbit (×4)
512 Mbit (×8)
512 Mbit (×4)
512 MB 1Rx8 PC2--6400P-666-12-F0
1 GB 1Rx4 PC2--6400P-666-12-H0
1 GB 2Rx8 PC2--6400P-666-12-G0
2 GB 2Rx4 PC2--6400P-666-12-L0
1 Rank ECC
1 Rank ECC
2 Ranks, ECC
2 Ranks, ECC
512 Mbit (×8)
512 Mbit (×4)
512 Mbit (×8)
512 Mbit (×4)
512 MB 1Rx8 PC2-6400P-555-12-F0
1 GB 1Rx4 PC2--6400P-555-12-H0
1 GB 2Rx8 PC2--6400P-555-12-G0
2 GB 2Rx4 PC2--6400P-555-12-L0
1 Rank ECC
1 Rank ECC
2 Ranks, ECC
2 Ranks, ECC
512 Mbit (×8)
512 Mbit (×4)
512 Mbit (×8)
512 Mbit (×4)
Compliance Code
2)
Description
SDRAM
Technology
1) All Product Type number end with a place code, designating the silicon die revision. Example: HYS72T64000HP–3.7–B, indicating Rev.
“B” dies are used for DDR2 SDRAM components. For all Qimonda DDR2 module and component nomenclature see
Chapter 6
of this data
sheet.
Rev. 1.1, 2007-03
03292006-EO3M-LEK7
4
Internet Data Sheet
HYS72T[64/128/256]xxxHP–[25F/2.5/3/3S/3.7]–B
240-Pin Registered DDR2 SDRAM
2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200R–444–12–F0”, where 4200P
means Registered DIMM modules (with Parity Bit) with 4.26 GB/sec Module Bandwidth and “444-12” means Column Address Strobe
(CAS) latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.2
and produced on the Raw Card “F”
TABLE 3
Address Format Table
DIMM
Density
512 MB
1 GB
1 GB
2 GB
2 GB
Module
Organization
64M
×72
128M
×72
128M
×72
256M
×72
256M
×72
Memory
Ranks
1
1
2
2
2
ECC/
Non-ECC
ECC
ECC
ECC
ECC
ECC
# of SDRAMs # of row/bank/column
bits
9
18
18
36
36
14/2/10
14/2/11
14/2/10
14/2/11
14/2/11
Raw
Card
F
H
G
J
L
TABLE 4
Components on Modules
Product Type
1)
HYS72T64000HP
HYS72T128000HP
HYS72T128020HP
HYS72T256220HP
DRAM Components
1)2)
HYB18T512800BF
HYB18T512400BF
HYB18T512800BF
HYB18T512400BF
DRAM Density
512 Mbit
512 Mbit
512 Mbit
512 Mbit
DRAM Organisation
512M × 8
512M × 4
512M × 8
512M × 4
1) Green Product
2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
Rev. 1.1, 2007-03
03292006-EO3M-LEK7
5
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