SN74LS51N3 datasheet, PDF - EEWORLD Datasheet

SN74LS51N3: DescriptionLS SERIES, DUAL 6-INPUT AND-OR-INVERT GATE, PDIP14; Categorylogic logic; File Size981KB，21 Pages; ManufacturerTexas Instruments; Websitehttp://www.ti.com.cn/

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SN74LS51N3 Overview

LS SERIES, DUAL 6-INPUT AND-OR-INVERT GATE, PDIP14

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
package instruction	DIP, DIP14,.3
Reach Compliance Code	not_compliant
Other features	ASYMMETRICAL I/P'S
series	LS
JESD-30 code	R-PDIP-T14
length	19.305 mm
Load capacitance (CL)	15 pF
Logic integrated circuit type	AND-OR-INVERT GATE
Number of functions	2
Number of entries	6
Number of terminals	14
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP14,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Maximum supply current (ICC)	2.8 mA
propagation delay (tpd)	20 ns
Certification status	Not Qualified
Schmitt trigger	NO
Maximum seat height	5.08 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	TTL
Temperature level	COMMERCIAL
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm
Base Number Matches	1

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