NM93CS06LZ/CS46LZ/CS56LZ/CS66LZ 256-/1024-/2048-/4096-Bit Serial EEPROM with Extended
Voltage (2.7V to 5.5V) and Data Protect ( MICROWIRE
™
Bus Interface)
NM93CS06LZ/CS46LZ/CS56LZ/CS66LZ
March 1997
NM93CS06LZ/CS46LZ/CS56LZ/CS66LZ
256-/1024-/2048-/4096-Bit Serial EEPROM with Extended
Voltage (2.7V to 5.5V) and Data Protect (MICROWIRE
™
Bus Interface)
General Description
The NM93CS06LZ/CS46LZ/CS56LZ/CS66LZ devices are
256/1024/2048/4096 bits, respectively, of non-volatile elec-
trically erasable memory divided into 16/64/128/256 x 16-bit
registers (addresses). The NM93CSxxLZ Family functions in
an extended voltage operating range and is fabricated using
Fairchild Semiconductor’s floating gate CMOS technology
for high reliability, high endurance and low power consump-
tion. N registers (N≤16, N≤64, N≤128, N≤256) can be pro-
tected against data modification by programming the Protect
Register with the address of the first register to be protected
against data modification. (All registers greater than, or
equal to, the selected address are then protected from fur-
ther change.) Additionally, this address can be “locked” into
the device, making all future attempts to change data impos-
sible.
These devices are available in both SO and TSSOP pack-
ages for small space considerations.
The serial interface that control these EEPROMs is MI-
CROWIRE compatible, providing simple interfacing to stan-
dard microcontrollers and microprocessors. There are a total
of 10 instructions, 5 which operate on the EEPROM memory
and 5 which operate on the Protect Register. The memory in-
structions are READ, WRITE, WRITE ALL, WRITE EN-
ABLE, and WRITE DISABLE. The Protect register instruc-
tions are PRREAD, PRWRITE, PRCLEAR, PRDISABLE and
PRENABLE.
Features
n
n
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n
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n
2.7V to 5.5V operation in all modes
Less than 1.0 µA standby current
Sequential register read
Write protection in a user-defined section of memory
Typical active current of 200 µA
Direct write: no erase before program
Reliable CMOS floating gate technology
MICROWIRE compatible serial I/O
Self-timed programming cycle
Device status indication during programming mode
40 years data retention
Endurance: 10
6
changes
Packages available: 8-pin SO, 8-pin DIP, 8-Pin TSSOP
Block Diagram
DS011807-1
© 1997 Fairchild Semiconductor Corporation
DS011807
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PrintDate=1997/08/29 PrintTime=12:23:19 10402 ds011807 Rev. No. 5 cmserv
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Functional Description
The extended voltage EEPROMs of the NM93CSxxLZ Fam-
ily have 10 instructions as described below. Note that MSB
of any instruction is a “1” and is viewed as a start bit in the in-
terface sequence. For the CS06 and CS46 the next 8 bits
carry the op code and the 6-bit address for register selection.
For the CS56 and CS66, the next 10 bits carry the op code
and the 8-bit address for register selection. All Data In sig-
nals are clocked into the device on the low-to-high SK tran-
sition.
Read and Sequential Register Read (READ):
The READ instruction outputs serial data on the D0 pin. After
a READ instruction is received, the instruction and address
are decoded, followed by data transfer from the selected
memory register into a 16-bit serial-out shift register. A
dummy bit (logical 0) precedes the 16-bit data output string.
Output data changes are initiated by a low to high transition
of the SK clock. In the
Sequential Read
mode of operation,
the memory automatically cycles to the next register after
each 16 data bits are clocked out. The dummy-bit is sup-
pressed in this mode and a continuous string of data is ob-
tained.
Write Enable (WEN):
When V
CC
is applied to the part, it “powers up” in the Write
Disable (WDS) state. Therefore, all programming modes
must be preceded by a Write Enable (WEN) instruction.
Once a Write Enable instruction is executed, programming
remains enabled until a Write Disable (WDS) instruction is
executed or V
CC
is removed from the part.
Write (WRITE):
The WRITE instruction is followed by 16 bits of data to be
written into the specified address. After the last bit of data is
allocated to the data-in (DI) pin, CS must be brought low be-
fore the next rising edge of the SK clock. This falling edge of
the CS initiates the self-timed programming cycle. The PE
pin
MUST
be held high while loading the WRITE instruction;
however, after loading the WRITE instruction, the PE pin be-
comes a “don’t care”. The D0 pin indicates the READY/
BUSY status of the chip if CS is brought high after the t
CS
in-
terval. D0 = logical 0 indicates that programming is still in
progress. D0 = logical 1 indicates that the register at the ad-
dress specified in the instruction has been written with the
data pattern specified in the instruction and that the part is
ready for another instruction.
Write All (WRALL):
The WRALL instruction is valid only when the Protect Regis-
ter has been cleared by executing a PRCLEAR instruction.
The WRALL instruction will simultaneously program all regis-
ters with the data pattern specified in the instruction. Like the
WRITE instruction, the PE pin
MUST
be held high while
loading the WRALL instruction; however, after loading the
WRITE instruction, the PE pin becomes a “don’t care”. As in
the WRITE mode, the DO pin indicates the READY/BUSY
status of the chip if CS is brought high after the t
CS
interval.
This function is DISABLED if the protect register is in use to
lock out a section memory.
Write Disable (WDS):
To protect against accidental data disturb, the WDS instruc-
tion disables all programming modes and should follow all
programming operations. Execution of a READ instruction is
independent of both the WEN and WDS instructions.
Note: For all protect register operations: If the PRE pin is not
held at V
IH
, all instructions will be applied to the EEPROM ar-
ray, rather than the Protect Register.
Protect Register Read (PRREAD):
The PRREAD instruction outputs the address stored in the
Protect Register on the DO pin. The PRE pin
MUST
be held
high while loading the instruction sequence. Following the
PRREAD instruction the 6- or 8-bit address stored in the
memory protect register is transferred to the serial out shift
register. As in the READ mode, a dummy bit (logical 0) pre-
cedes the 6- or 8-bit address string.
Protect Register Enable (PREN):
The PREN instruction is used to enable the PRCLEAR,
PRWRITE, and PRDS modes. Before the PREN mode can
be entered, the part must be in the Write Enable (WEN)
mode. Both the PRE and PE pins
MUST
be held high while
loading the instruction sequence.
Note that a PREN instruction must
immediately
precede a
PRCLEAR, PRWRITE, or PRDS instruction.
Protect Register Clear (PRCLEAR):
The PRCLEAR instruction clears the address stored in the
Protect Register and therefore enables
all
registers for the
WRITE and WRALL instruction. The PRE and PE pins
must
be held high while loading the instruction sequence; how-
ever, after loading the PRCLEAR instruction, the PRE and
PE pins become “don’t care”. Note that a PREN instruction
must
immediately
precede a PRCLEAR instruction.
Please note that the PRCLEAR instruction and the
PRWRITE instruction will both program the Protect Register
with all 1s. However, the PRCLEAR instruction will allow the
LAST register to be programmed, whereas the PRWRITE in-
struction = all 1s will PREVENT the last register from being
programmed. In addition, the PRCLEAR instruction will allow
the use of the WRALL command, where the PRWRITE = all
1s will lock out the Bulk programming opcode.
Protect Register Write (PRWRITE):
The PRWRITE instruction is used to write into the Protect
Register the address of the first register to be protected. Af-
ter the PRWRITE instruction is executed, all memory regis-
ters whose addresses are greater than or equal to the ad-
dress specified in the Protect Register are protected from the
WRITE operation. Note that before executing a PRWRITE
instruction, the Protect Register must first be cleared by ex-
ecuting a PRCLEAR operation and the PRE and PE pins
must
be held high while loading the instruction; however, af-
ter loading the PRWRITE instruction, the PRE and PE pins
become “don’t care”. Note that a PREN instruction must
im-
mediately
precede a PRWRITE instruction.
Protect Register Disable (PRDS):
The PRDS instruction is a ONE TIME ONLY instruction
which renders the Protect Register unalterable in the future.
Therefore, the specified registers become
PERMANENTLY
protected against data changes. As in the PRWRITE instruc-
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PrintDate=1997/08/29 PrintTime=12:23:29 10402 ds011807 Rev. No. 5
cmserv
Proof
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