UPD44165364F5-E30-EQ1 datasheet, PDF

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UPD44165364F5-E30-EQ1: DescriptionQDR SRAM, 512KX36, 0.27ns, CMOS, PBGA165, 13 X 15 MM, PLASTIC, FBGA-165; Categorystorage storage; File Size219KB，32 Pages; ManufacturerNEC Electronics

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UPD44165364F5-E30-EQ1 Overview

QDR SRAM, 512KX36, 0.27ns, CMOS, PBGA165, 13 X 15 MM, PLASTIC, FBGA-165

UPD44165364F5-E30-EQ1 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	BGA
package instruction	BGA,
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Base Number Matches	1

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PRELIMINARY DATA SHEET

PD44165084, 44165184, 44165364

18M-BIT QDR

II SRAM

4-WORD BURST OPERATION

MOS INTEGRATED CIRCUIT

Description

The

PD44165084 is a 2,097,152-word by 8-bit, the

PD44165184 is a 1,048,576-word by 18-bit and the

PD44165364

is a 524,288-word by 36-bit synchronous quad data rate static RAM fabricated with advanced CMOS technology using full

CMOS six-transistor memory cell.

The

PD44165084,

PD44165184 and

PD44165364 integrates unique synchronous peripheral circuitry and a

burst counter. All input registers controlled by an input clock pair (K and /K) and are latched on the positive edge of K

and /K.

These products are suitable for applications which require synchronous operation, high speed, low voltage, high density

and wide bit configuration.

These products are packaged in 165-pin PLASTIC FBGA.

Features

•

1.8 ± 0.1 V power supply and HSTL I/O

•

DLL circuitry for wide output data valid window and future frequency scaling

•

Separate independent read and write data ports with concurrent transactions

•

100% bus utilization DDR READ and WRITE operation

•

Four-tick burst for reduced address frequency

•

Two input clocks (K and /K) for precise DDR timing at clock rising edges only

•

Two output clocks (C and /C) for precise flight time

and clock skew matching-clock and data delivered together to receiving device

•

Internally self-timed write control

•

Clock-stop capability with

s restart

•

User programmable impedence output

•

Fast clock cycle time : 3.0 ns (333 MHz), 3.3 ns (300 MHz), 4.0 ns (250 MHz) , 5.0 ns (200 MHz) , 6.0 ns (167 MHz)

•

Simple control logic for easy depth expansion

•

JTAG boundary scan

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for

availability and additional information.

Document No. M15825EJ2V0DS00 (2nd edition)

Date Published April 2002 NS CP(K)

Printed in Japan

The mark

shows major revised points.

2001

UPD44165364F5-E30-EQ1 Related Products

	UPD44165364F5-E30-EQ1	UPD44165084F5-E33-EQ1	UPD44165084F5-E30-EQ1	UPD44165364F5-E33-EQ1	UPD44165184F5-E33-EQ1	UPD44165184F5-E30-EQ1
Description	QDR SRAM, 512KX36, 0.27ns, CMOS, PBGA165, 13 X 15 MM, PLASTIC, FBGA-165	QDR SRAM, 2MX8, 0.29ns, CMOS, PBGA165, 13 X 15 MM, PLASTIC, FBGA-165	QDR SRAM, 2MX8, 0.27ns, CMOS, PBGA165, 13 X 15 MM, PLASTIC, FBGA-165	QDR SRAM, 512KX36, 0.29ns, CMOS, PBGA165, 13 X 15 MM, PLASTIC, FBGA-165	QDR SRAM, 1MX18, 0.29ns, CMOS, PBGA165, 13 X 15 MM, PLASTIC, FBGA-165	QDR SRAM, 1MX18, 0.27ns, CMOS, PBGA165, 13 X 15 MM, PLASTIC, FBGA-165
Is it lead-free?	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Parts packaging code	BGA	BGA	BGA	BGA	BGA	BGA
package instruction	BGA,	BGA,	BGA,	BGA,	BGA,	BGA,
Contacts	165	165	165	165	165	165
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compli
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
Maker	-	-	NEC Electronics	NEC Electronics	NEC Electronics	NEC Electronics

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