U634H256
PowerStore
32K x 8 nvSRAM
Features
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Packages: PDIP32 (600 mil)
Description
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SOP32 (300 mil)
High-performance CMOS non-
volatile static RAM 32768 x 8 bits
25, 35 and 45 ns Access Times
10, 15 and 20 ns Output Enable
Access Times
I
CC
= 15 mA at 200 ns Cycle Time
Automatic STORE to EEPROM
on Power Down using external
capacitor
Hardware or Software initiated
STORE
(STORE Cycle Time < 10 ms)
Automatic STORE Timing
10
5
STORE cycles to EEPROM
10 years data retention in
EEPROM
Automatic RECALL on Power Up
Software RECALL Initiation
(RECALL Cycle Time < 20
µs)
Unlimited RECALL cycles from
EEPROM
Single 5 V
±
10 % Operation
Operating temperature ranges:
0 to 70
°C
-40 to 85
°C
CECC 90000 Quality Standard
ESD characterization according
MIL STD 883C M3015.7-HBM
(classification see IC Code
Numbers)
The U634H256 has two separate
modes of operation: SRAM mode
and nonvolatile mode. In SRAM
mode, the memory operates as an
ordinary static RAM. In nonvolatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
mode SRAM functions are disab-
led.
The U634H256 is a fast static RAM
(25, 35, 45 ns), with a nonvolatile
electrically
erasable
PROM
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation) take place
automatically upon power down
using charge stored in an external
100
µF
capacitor.
Transfers from the EEPROM to the
SRAM (the RECALL operation) take
place automatically on power up.
The U634H256 combines the high
performance and ease of use of a
fast SRAM with nonvolatile data
integrity.
STORE cycles also may be initiated
under user control via a software
sequence or via a single pin (HSB).
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or write
accesses intervene in the sequence
or the sequence will be aborted.
RECALL cycles may also be initia-
ted by a software sequence.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvolatile
information is transferred into the
SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
Pin Configuration
Pin Description
VCAP
A14
A12
A7
A6
A5
A4
A3
n.c.
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PDIP
SOP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCCX
HSB
W
A13
A8
A9
A11
G
n.c.
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Signal Name
A0 - A14
DQ0 - DQ7
E
G
W
VCCX
VSS
VCAP
HSB
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
Capacitor
Hardware Controlled Store/Busy
Top View
December 12, 1997
1
U634H256
Block Diagram
EEPROM
Array
A5
A6
A7
A8
A9
A11
A12
A13
A14
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
E
W
Input Buffers
STORE
Row Decoder
SRAM
Array
512 Rows x
64 x 8 Columns
Store/
Recall
Control
V
CCX
V
SS
V
CA P
Power
Control
RECALL
V
CCX
V
CA P
HSB
Column I/O
Column Decoder
Software
Detect
A0 - A13
A0 A1 A2 A3 A4 A10
G
Truth Table for SRAM Operations
Operating Mode
Standby/not selected
Internal Read
Read
Write
*
H or L
Characteristics
All voltages are referenced to V
SS
= 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of
≤
5 ns, measured between 10 % and 90 % of V
I
, as well as
input levels of V
IL
= 0 V and V
IH
= 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the t
dis
-times and t
en
-times, in which cases transition is measured
±
200 mV from steady-state voltage.
E
H
L
L
L
HSB
H
H
H
H
W
*
H
H
L
G
*
H
L
*
DQ0 - DQ7
High-Z
High-Z
Data Outputs Low-Z
Data Inputs High-Z
Absolute Maximum Ratings
a
Power Supply Voltage
Input Voltage
Output Voltage
Power Dissipation
Operating Temperature
Storage Temperature
a:
Symbol
V
CC
V
I
V
O
P
D
C-Type
K-Type
T
a
T
stg
Min.
-0.5
-0.3
-0.3
Max.
7
V
CC
+0.5
V
CC
+0.5
1
Unit
V
V
V
W
°C
°C
°C
0
-40
-65
70
85
150
Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2
December 12, 1997
U634H256
Recommended
Operating Conditions
Power Supply Voltage
b
Input Low Voltage
Input High Voltage
Symbol
V
CC
V
IL
V
IH
-2 V at Pulse Width
10 ns permitted
Conditions
Min.
4.5
-0.3
2.2
Max.
5.5
0.8
V
CC
+0.3
Unit
V
V
V
C-Type
DC Characteristics
Operating Supply Current
c
Symbol
I
CC1
V
CC
V
IL
V
IH
t
c
t
c
t
c
Average Supply Current during
STORE
c
I
CC2
V
CC
E
W
V
IL
V
IH
V
CC
V
IL
V
IH
V
CC
E
t
c
t
c
t
c
Operating Supply Current
at t
cR
= 200 ns
c
(Cycling CMOS Input Levels)
Standby Supply Curent
d
(Stable CMOS Input Levels)
I
CC3
V
CC
W
V
IL
V
IH
V
CC
E
V
IL
V
IH
Conditions
Min.
= 5.5 V
= 0.8 V
= 2.2 V
= 25 ns
= 35 ns
= 45 ns
= 5.5 V
≤
0.2 V
≥
V
CC
-0.2 V
≤
0.2 V
≥
V
CC
-0.2 V
= 4.5 V
= 0.2 V
≥
V
CC
-0.2 V
= 5.5 V
= V
IH
= 25 ns
= 35 ns
= 45 ns
= 5.5 V
≥
V
CC
-0.2 V
≤
0.2 V
≥
V
CC
-0.2 V
= 5.5 V
≥
V
CC
-0.2 V
≤
0.2 V
≥
V
CC
-0.2 V
40
36
33
15
95
75
65
6
Max.
K-Type
Unit
Min.
Max.
100
80
70
7
mA
mA
mA
mA
Average Supply Current during
PowerStore
Cycle
Standby Supply Current
d
(Cycling TTL Input Levels)
I
CC4
4
4
mA
I
CC(SB)1
42
38
35
15
mA
mA
mA
mA
I
CC(SB)
3
3
mA
b: V
CC
reference levels throughout this datasheet refer to V
CCX
if that is where the power supply connection is made, or V
CAP
if V
CCX
is con-
nected to ground.
c: I
CC1
and I
CC3
are depedent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
The current I
CC1
is measured for WRITE/READ - ratio of 1/2.
I
CC2
is the average current required for the duration of the STORE cycle (STORE Cycle Time).
d: Bringing E
≥
V
IH
will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION able.
The current I
CC(SB)1
is measured for WRITE/READ - ratio of 1/2.
December 12, 1997
3
U634H256
C-Type
DC Characteristics
Symbol
V
CC
I
OH
I
OL
V
CC
V
OH
V
OL
V
CC
High
Low
Output Leakage Current
High at Three-State- Output
Low at Three-State- Output
I
OHZ
I
OLZ
I
IH
I
IL
V
IH
V
IL
V
CC
V
OH
V
OL
Conditions
Min.
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Input Leakage Current
V
OH
V
OL
I
OH
I
OL
= 4.5 V
=-4 mA
= 8 mA
= 4.5 V
= 2.4 V
= 0.4 V
= 5.5 V
= 5.5 V
= 0V
= 5.5 V
= 5.5 V
= 0V
1
-1
-1
1
µA
µA
1
-1
-1
1
µA
µA
2.4
0.4
-4
8
8
Max.
Min.
2.4
0.4
-4
Max.
V
V
mA
mA
K-Type
Unit
SRAM MEMORY OPERATIONS
Symbol
Alt.
t
AVAV
t
AVQV
t
ELQV
t
GLQV
t
EHQZ
t
GHQZ
t
ELQX
t
GLQX
t
AXQX
t
ELICCH
t
EHICCL
IEC
t
cR
t
a(A)
t
a(E)
t
a(G)
t
dis(E)
t
dis(G)
t
en(E)
t
en(G)
t
v(A)
t
PU
t
PD
5
0
3
0
25
Min.
25
25
25
10
10
10
5
0
3
0
35
25
Max.
Min.
35
35
35
15
13
13
5
0
3
0
45
35
Max.
45
Unit
Min.
45
45
45
20
15
15
Max.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
No.
1
2
3
4
5
6
7
8
9
Switching Characteristics
Read Cycle
Read Cycle Time
f
Address Access Time to Data Valid
g
Chip Enable Access Time to Data Valid
Output Enable Access Time to Data Valid
E HIGH to Output in High-Z
h
G HIGH to Output in High-Z
h
E LOW to Output in Low-Z
G LOW to Output in Low-Z
Output Hold Time after Address Change
10 Chip Enable to Power Active
e
11 Chip Disable to Power Standby
d, e
e:
f:
g:
h:
Parameter guaranteed but not tested.
Device is continuously selected with E and G both LOW.
Address valid prior to or coincident with E transition LOW.
Measured
±
200 mV from steady state output voltage.
4
December 12, 1997
U634H256
Read Cycle 1: Ai-controlled (during Read cycle: E = G = V
IL
, W = V
IH
)
f
1
t
cR
Ai
Address Valid
2
t
a(A )
DQi
Output
Previous
Data Valid
9
t
v(A)
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
Output Data
Valid
Read Cycle 2: G-, E-controlled (during Read cycle: W = V
IH
)
g
1
t
cR
Ai
Address Valid
2
t
a(A)
11
t
PD
5
t
dis(E)
E
G
DQi
Output
High Impedance
ACTIVE
STANDBY
7
t
en(E)
3
t
a(E)
4
t
a(G)
8
t
en(G)
10
t
PU
6
t
dis(G)
AAAAAAAAAAAA
Output Data
AAAAAAAAAAAA
AAAAAAAAAAAA
Valid
AAAAAAAAAAAA
I
CC
No.
Switching Characteristics
Write Cycle
Symbol
Alt. #1 Alt. #2
t
AVAV
t
WLWH
t
WLEH
t
AVWL
t
AVWH
t
ELWH
t
ELEH
t
DVWH
t
WHDX
t
WHAX
t
WLQZ
t
WHQX
t
DVEH
t
EHDX
t
EHAX
t
AVEL
t
AVEH
t
AVAV
IEC
t
cW
t
w(W)
t
su(W)
t
su(A)
t
su(A-WH)
t
su(E)
t
w(E)
t
su(D)
t
h(D)
t
h(A)
t
dis(W)
t
en(W)
5
25
35
45
Unit
Min. Max. Min. Max. Min. Max.
25
20
20
0
20
20
20
10
0
0
10
5
35
25
25
0
25
25
25
12
0
0
13
5
45
30
30
0
30
30
30
15
0
0
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12 Write Cycle Time
13 Write Pulse Width
14 Write Pulse Width Setup Time
15 Address Setup Time
16 Address Valid to End of Write
17 Chip Enable Setup Time
18 Chip Enable to End of Write
19 Data Setup Time to End of Write
20 Data Hold Time after End of Write
21 Address Hold after End of Write
22 W LOW to Output in High-Z
h, i
23 W HIGH to Output in Low-Z
December 12, 1997
5
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