AT84CS001
10-bit 2.2 Gsps 1:4 DMUX
Datasheet
Features
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High-speed ADC Family Companion Chip
Selectable 1:2 or 1:4 DMUX Ratio
Power Consumption: 2.7W
LVDS Compatible Differential Data and Clock Inputs (100Ω Terminated)
LVDS Compatible Differential Data and Data Ready Outputs
Staggered or Simultaneous Data Outputs
– 11
th
Bit = Ports A, B, C and D Clock in Staggered Mode
Selectable Active Edge for Input and Output Clocks:
– Only Rising: CLK and DR Mode
– Rising and Falling: CLK/2 and DR/2 Mode
Fine Tuning of Input Clock Path Delay
– Compensation of External Data and Clock Path Misalignment and Skews
– Once Tuned, Setting is Valid over Full Operating Frequency and Over Full Specified Temperature Range
Additional 11
th
Bit (Example: for Out-of-range Bit)
Built-in Self Test (BIST)
Stand-alone Tunable Delay Cell
Power Supplies: V
CCD
= 3.3V (Digital), V
PLUSD
= 2.5V (Outputs)
Power Consumption Reduction Mode: 1.15W
EBGA240 Package
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Screening
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Temperature Range:
– - 40°C < T
C
; T
J
< 110°C (Industrial Grade)
Applications
This DMUX enables users to process high-speed output data streams from fast analog-to-digital converters down to stan-
dard FPGA processor speed.
Description
The AT84CS001 is a monolithic high-speed demultiplexer, used to lower a 10-bit data stream of up to 2.2 Gsps guaranteed
rate by a selectable 4 or 2 ratio (a 1:8 ratio might be achieved by interleaving two DMUXes).
The DMUX is a companion chip designed to fit perfectly with all of e2v’s high-speed ADCs and is capable of tracking the
ADC’s output sampling rate over all operating frequency and temperature ranges.
Thanks to its LVDS buffers, this DMUX can easily be interfaced with standard high-speed FPGAs (100Ω differentially
terminated).
The AT84CS001 has the same footprint as e2v’s TS81102G0 DMUX, with a very similar pinout. Minimum re-design efforts
are required to use this low-power DMUX. An application note
Migration from AT84AS008 to EV10AS008B
reference 0810,
is available to assist in migrating from the TS81102G0 to the AT84CS001.
Visit our website: www.e2v.com
for the latest version of the datasheet
e2v semiconductors SAS 2008
0809D–BDC–04/08
AT84CS001
1. Block Diagram
Figure 1-1.
Block Diagram
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AT84CS001
2. Overview
The AT84CS001 is a monolithic high-speed demultiplexer (DMUX) using high-speed e2v technology.
It enables the user to lower a 10-bit stream of 2.2 Gsps maximum by a factor of two or four. One can
obtain a 1:8 ratio by using two interleaved AT84CS001 devices. The maximum input data rate is 2.2
Gsps in 1:4 ratio and 1.8 Gsps in 1:2 ratio.
The AT84CS001 DMUX is capable of processing an 11-bit data flow. The additional 11
th
bit (IOR, IORN)
might be connected for example to the out-of-range bit of a 10-bit ADC.
The input and output clocks as well as the input and output data are LVDS compatible. Digital inputs are
100Ω differentially terminated on chip. Digital output buffers shall be terminated by a 100Ω differential
ASIC load.
The improved architecture of the DMUX facilitates interfacing with high-speed ADCs operating at up to
2.2 Gsps. A tunable delay cell is integrated in serial with the clock input: it can be used to tune the delay
between the data and clock paths namely for high speed rates and in the case of misalignment or skews
between the external clock path and the data path. The delay is controlled by means of the CLKDACTRL
analog control input. The tunable delay ranges from -250 ps to 250 ps for CLKDACTRL varying from
V
CCD
/2 to (2 × V
CCD
)/3.
Two modes can be selected for the clock input (CLK and CLK/2) and the clock output (DR and DR/2):
• CLK and DR mode: Only the rising edges of the input (CLK,CLKN) and output (DR, DRN) clocks are
active. The input (or output) clock rate remains the same as the input or output data rate.
• CLK/2 and DR/2 mode: Both the rising and falling edges of the input (CLK,CLKN) and output (DR,
DRN) clocks are active. The input (or output) clock rate is half the input or output data rate.
The data outputs can be received at the DMUX output in two different modes:
• Staggered: even and odd bits are output with half a data period delay
• Simultaneous: even and odd bits are output at the same time
The AT84CS001 DMUX is started by the ASYNCRST control input that acts as a master asynchronous
reset for the device. Once reset, there is no loss of synchronization over an indefinite time period, there-
fore no additional incoming synchronous reset signal is required.
The power consumption of the AT84CS001 is 2.7W and can be reduced by approximately 60% of its
nominal value by means of the SLEEP control input.
A standalone delay cell is provided. It features a typical 550 ps tuning range (± 275 ps around the center
value of DACTRL analog control input).
A Built-in Self Test (BIST) is implemented for rapid debugging of the DMUX.
The AT84CS001 DMUX is a companion chip designed to fit perfectly with all of e2v’s high-speed ADCs.
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AT84CS001
3. Description of Main Functions
Table 3-1.
Name
V
CCD
V
PLUSD
GND
CLK, CLKN
I0, I0N…I9, I9N
IOR, IORN
DR/DRN
A0, A0N…A9, A9N
AOR/DRAN,
AORN/DRA
B0, B0N…B9, B9N
BOR/DRBN,
BORN/DRB
C0, C0N…C9, C9N
COR/DRCN,
CORN/DRC
Description of Main Functions
Function
Digital 3.3V power supply
D0, D0N...D9, D9N
Output 2.5V power supply
Ground
Input clock signals
Input data
DACTRL
Additional input bit
Output clock signals
Output data port A
SLEEP
Additional output bit port A or port A
output clock in staggered mode
Output data port B
DRTYPE
Additional output bit port B or port B
output clock in staggered mode
Output data port C
Additional output bit port C or port C
output clock in staggered mode
STAGG
BIST
Output clock type selection signal
Staggered mode selection for data
outputs
Built-in Self Test enable
RS
CLKTYPE
Sleep mode selection signal
DMUX ratio selection signal
Input clock type selection signal
CLKDACTRL
DAEN
ASYNCRST
Control signal for standalone delay cell
Control signal for clock delay cell
Enable signal for standalone delay cell
Asynchronous reset signal
DOR/DRDN,
DORN/DRD
DAO, DAON
DAI, DAIN
Additional output bit port D or port D
output clock in staggered mode
Output signals for stand-alone delay cell
Input signals for stand-alone delay cell
Output data port D
Name
Function
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AT84CS001
Figure 3-1.
Device Pinout
VCCD
VPLUSD
20
[A0…A9]
[A0N…A9N]
[I0…I9]
[I0N…I9N]
CLK, CLKN
ASYNCRST
DACTRL
CLKDACTRL
20
2
2
AOR/DRAN
AORN/DRA
20
[B0…B9]
2
2
20
AT84CS001
2
20
2
2
2
DAI, DAIN
SLEEP
STAGG
CLKTYPE
RS
DAEN
BIST
DRTYPE
[B0N…B9N]
BOR/DRBN
BORN/DRB
[C0…C9]
[C0N…C9N]
COR/DRCN
CORN/DRC
[D0…D9]
[D0N…D9N]
DOR/DRDN
DORN/DRD
DAO, DAON
DR, DRN
GND
3.1
Control Signal Settings
The ASYNCRST, SLEEP, DAEN, STAGG, BIST, RS, CLKTYPE and DRTYPE control signals use the
same static input buffer.
ASYNCRST is activated on logic HIGH (tied/switched to V
CCD
= 3.3V, or 10 kΩ to ground, or left float-
ing), and deactivated on logic LOW (grounded).
SLEEP, DAEN, STAGG, BIST are activated on logic LOW (10Ω grounded), and deactivated on logic
HIGH (10 kΩ to ground, or tied to V
CCD
= 3.3V, or left floating).
Figure 3-2.
Control Signal Settings
Control
Signal Pin
Control
Signal Pin
Not
Connected
Control
Signal Pin
10Ω
10 KΩ
GND
Active Low Level ('0')
GND
Inactive High Level ('1')
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