PSD413A2-12JI datasheet, PDF - EEWORLD Datasheet

PSD413A2-12JI: DescriptionParallel I/O Port, 40 I/O, CMOS, PQCC68,; CategoryThe embedded processor and controller Microcontrollers and processors; File Size4MB，97 Pages; ManufacturerWaferscale Integration Inc.

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PSD413A2-12JI Overview

Parallel I/O Port, 40 I/O, CMOS, PQCC68,

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Reach Compliance Code	unknown
Maximum access time	1.2e-7 ns
Other features	GENERAL PURPOSE ZPLD
maximum clock frequency	35.71 MHz
External data bus width	8
JESD-30 code	S-PQCC-J68
JESD-609 code	e0
Number of I/O lines	40
Number of ports	5
Number of terminals	68
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC68,1.0SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Certification status	Not Qualified
ROM size (bits)	1024 Bits
Maximum standby current	0.00002 A
Maximum slew rate	40 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
UV erasable	N
uPs/uCs/peripheral integrated circuit type	PARALLEL IO PORT, GENERAL PURPOSE
Base Number Matches	1

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

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