EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
M5M4V4265CTP-5S Parametric
Parameter Name
Attribute value
Is it lead-free?
Contains lead
Is it Rohs certified?
incompatible
Maker
Mitsubishi
Parts packaging code
TSOP2
package instruction
TSOP2, TSOP40/44,.46,32
Contacts
44
Reach Compliance Code
unknow
ECCN code
EAR99
access mode
FAST PAGE WITH EDO
Maximum access time
50 ns
Other features
RAS ONLY/CAS BEFORE RAS/HIDDEN/SELF REFRESH
Spare memory width
8
I/O type
COMMON
JESD-30 code
R-PDSO-G40
JESD-609 code
e0
length
18.41 mm
memory density
4194304 bi
Memory IC Type
EDO DRAM
memory width
16
Number of functions
1
Number of ports
1
Number of terminals
40
word count
262144 words
character code
256000
Operating mode
ASYNCHRONOUS
Maximum operating temperature
70 °C
Minimum operating temperature
organize
256KX16
Output characteristics
3-STATE
Package body material
PLASTIC/EPOXY
encapsulated code
TSOP2
Encapsulate equivalent code
TSOP40/44,.46,32
Package shape
RECTANGULAR
Package form
SMALL OUTLINE, THIN PROFILE
Peak Reflow Temperature (Celsius)
NOT SPECIFIED
power supply
3.3 V
Certification status
Not Qualified
refresh cycle
512
Maximum seat height
1.2 mm
self refresh
YES
Maximum standby current
0.0001 A
Maximum slew rate
0.135 mA
Maximum supply voltage (Vsup)
3.6 V
Minimum supply voltage (Vsup)
3 V
Nominal supply voltage (Vsup)
3.3 V
surface mount
YES
technology
CMOS
Temperature level
COMMERCIAL
Terminal surface
Tin/Lead (Sn/Pb)
Terminal form
GULL WING
Terminal pitch
0.8 mm
Terminal location
DUAL
Maximum time at peak reflow temperature
NOT SPECIFIED
width
10.16 mm
M5M4V4265CTP-5S Preview
MITSUBISHI LSIs
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
DESCRIPTION
This is a family of 262144-word by 16-bit dynamic RAMs with EDO
mode fuction, fabricated with the high performance CMOS
process, and is ideal for the buffer memory systems of personal
computer graphics and HDD where high speed, low power
dissipation, and low costs are essential. The use of double-layer
metalization process technology and a single-transistor dynamic
storage stacked capacitor cell provide high circuit density at
reduced costs. The lower supply (3.3V) operation, due to the
optimization of transistor structure, provides low power dissipation
while maintaining high speed operation. Multiplexed address inputs
permit both a reduction in pins and an increase in system
densities. Self or extended refresh current is low enough for
battery back-up application. This device has 2CAS and 1W
terminals with a refresh cycle of 512 cycles every 8.2ms.
PIN CONFIGURATION (TOP VIEW)
(3.3V)V
CC
DQ
1
DQ
2
DQ
3
DQ4
(3.3V)V
CC
DQ
5
DQ
6
DQ
7
1
2
3
4
5
6
7
8
9
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
S
S(0V)
DQ
16
DQ
15
DQ
14
DQ
13
V
SS
(0V)
DQ
12
DQ
11
DQ
10
DQ
9
NC
LCAS
UCAS
OE
A
8
A
7
A
6
A
5
A
4
V
SS
(0V)
DQ
8 10
FEATURES
Type name
M5M4V4265CXX-5,-5S
M5M4V4265CXX-6,-6S
M5M4V4265CXX-7,-7S
RAS
CAS
Address
access
access access
time
time
time
(max.ns) (max.ns) (max.ns)
Power
OE
Cycle
dissipa-
access
time
tion
time
(max.ns) (min.ns) (typ.mW)
NC
11
NC
12
W
13
RAS
14
NC
15
A
0 16
A
1 17
A
2 18
A
3 19
(3.3V)V
CC 20
50
60
70
13
15
20
25
30
35
13
15
20
90
110
130
408
363
333
XX=TP,J
Standard 40 pin SOJ, 44 pin TSOP (II)
Single 3.3±0.3V supply
Low stand-by power dissipation
CMOS Input level
1.8mW (Max)
CMOS Input level
360µW (Max) *
Operating power dissipation
M5M4V4265CXX-5,-5S
486mW (Max)
M5M4V4265CXX-6,-6S
432mW (Max)
M5M4V4265CXX-7,-7S
396mW (Max)
Self refresh capability *
Self refresh current
100µA (Max)
Extended refresh capability
Extended refresh current
100µA (Max)
EDO mode (512-column random access), Read-modify-write, RAS-
only refresh, CAS before RAS refresh, Hidden refresh capabilities.
Early-write mode, OE and W to control output buffer impedance
512 refresh cycles every 8.2ms (A
0
~A
8
)
512 refresh cycles every 128ms (A
0
~A
8
) *
Byte or word control for Read/Write operation (2CAS, 1W type)
* : Applicable to self refresh version (M5M4V4265CJ,TP-5S,-6S,
-7S : option) only
Outline 40P0K (400mil SOJ)
(3.3V)V
CC
DQ
1
DQ
2
DQ
3
DQ4
(3.3V)V
CC
DQ
5
DQ
6
DQ
7
1
2
3
4
5
6
7
8
9
44
43
42
41
40
39
38
37
36
35
V
S
S(0V)
DQ
16
DQ
15
DQ
14
DQ
13
V
SS
(0V)
DQ
12
DQ
11
DQ
10
DQ
9
DQ
8 10
APPLICATION
Microcomputer memory, Refresh memory for CRT, Frame buffer
memory for CRT
NC
13
NC
14
32
31
30
29
28
27
26
25
24
23
NC
LCAS
UCAS
OE
A
8
A
7
A
6
A
5
A
4
V
SS
(0V)
PIN DESCRIPTION
Pin name
A
0
~A
8
DQ
1
~DQ
16
RAS
LCAS
UCAS
W
OE
V
CC
V
SS
1
Function
Address inputs
Data inputs / outputs
Row address strobe input
Lower byte control
column address strobe input
Upper byte control
column address strobe input
Write control input
Output enable input
Power supply (+3.3V)
Ground (0V)
W
15
RAS
16
NC
17
A
0 18
A
1 19
A
2 20
A
3 21
(3.3V)V
CC 22
Outline 44P3W-R (400mil TSOP Nomal Bend)
NC : NO CONNECTION
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
FUNCTION
In addition to EDO Mode, normal read, write and read-modify-
write operations the M5M4V4265CXX provides a number of other
functions, e.g., RAS-only refresh, and delayed-write. The input
conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
Operation
Lower byte read
Upper byte read
Word read
Lower byte write
Upper byte write
Word write
RAS only refresh
Hidden refresh
CAS before RAS (Extended *) refresh
Inputs
RAS
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
NAC
LCAS
ACT
NAC
ACT
ACT
NAC
ACT
NAC
ACT
ACT
ACT
DNC
UCAS
NAC
ACT
ACT
NAC
ACT
ACT
NAC
ACT
ACT
ACT
DNC
W
NAC
NAC
NAC
ACT
ACT
ACT
DNC
NAC
DNC
DNC
DNC
OE
ACT
ACT
ACT
NAC
NAC
NAC
DNC
ACT
DNC
DNC
DNC
DQ
1
~DQ
8
D
OUT
OPN
D
OUT
D
IN
DNC
D
IN
OPN
D
OUT
OPN
OPN
OPN
Input/Output
DQ
9
~DQ
16
OPN
D
OUT
D
OUT
DNC
D
IN
D
IN
OPN
D
OUT
OPN
OPN
OPN
Self refresh *
Stand-by
Note : ACT : active, NAC : nonactive, DNC : don' t care, OPN : open
BLOCK DIAGRAM
ROW ADDRESS
STROBE INPUT
RAS
LOWER BYTE CONTROL
COLUMN ADDRESS
LCAS
STROBE INPUT
UPPER BYTE CONTROL
UCAS
COLUMN ADDRESS
STROBE INPUT
WRITE CONTROL
INPUT
V
CC
(3.3V)
CLOCK GENERATOR
CIRCUIT
LOWER
UPPER
(8)LOWER
DATA IN
BUFFER
V
SS
(0V)
DQ
1
DQ
2
DQ
8
W
(8)LOWER
DATA OUT
BUFFER
LOWER DATA
INPUTS /
OUTPUTS
V
CC
(3.3V)
V
SS
(0V)
A
0
~A
8
COLUMN DECODER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
(8)UPPER
DATA IN
BUFFER
SENSE REFRESH
AMPLIFIER & I /O CONTROL
DQ
9
DQ
10
DQ
16
ADDRESS INPUTS
ROW &
COLUMN
ADDRESS
BUFFER
UPPER DATA
INPUTS /
OUTPUTS
ROW
A
0
~
A
8
DECODER
MEMORY CELL
(4,194,304 BITS)
(8)UPPER
DATA OUT
BUFFER
V
CC
(3.3V)
V
SS
(0V)
OE
OUTPUT ENABLE
INPUT
2
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
I
O
P
d
T
opr
T
stg
Parameter
Supply voltage
Input voltage
Output voltage
Output current
Power dissipation
Operating temperature
Storage temperature
Conditions
With respect to V
SS
Ratings
-0.5~4.6
-0.5~4.6
-0.5~4.6
50
1000
0~70
-65~150
Unit
V
V
V
mA
mW
˚C
˚C
Ta=25˚C
RECOMMENDED OPERATING CONDITIONS
(Ta=0~70˚C, unless otherwise noted)
Symbol
V
CC
V
SS
V
IH
V
IL
Parameter
Supply voltage
Supply voltage
High-level input voltage, all inputs
Low-level input voltage, all inputs
Min
3.0
0
2.0
-0.3
Limits
Nom
3.3
0
Max
3.6
0
V
CC
+0.3
(Note 1)
Unit
V
V
V
V
0.8
Note 1 : All voltage values are with respect to V
SS.
ELECTRICAL CHARACTERISTICS
(Ta=0~70˚C, V
CC
=3.3±0.3V, V
SS
=0V, unless otherwise noted)
(Note 2)
Symbol
V
OH
V
OL
I
OZ
I
I
I
CC1(AV)
Parameter
High-level output voltage
Low-level output voltage
Off-state output current
Input current
Average supply current
from Vcc, operating
(Note 3,4,5)
M5M4V4265C-5,-5S
M5M4V4265C-6,-6S
M5M4V4265C-7,-7S
Test conditions
I
OH
=-2mA
I
OL
=2mA
Q floating 0V≤V
OUT
≤V
CC
0V
≤
V
IN
≤
V
CC
+0.3V, Other inputs pins=0V
RAS, CAS cycling
t
RC
=t
WC
=min.
output open
RAS= CAS =V
IH
, output open
Min
2.4
0
-5
-5
Limits
Typ
Max
V
CC
0.4
5
5
135
120
110
2
0.5
0.1 *
125
110
95
125
110
95
115
100
85
Unit
V
V
µA
µA
mA
I
CC2
Supply current from V
CC
, stand-by
(Note 6) RAS= CAS≥V
CC
-0.2V
output open
RAS cycling, CAS=V
IH
t
RC
=min.
output open
RAS=V
IL
, CAS cycling
t
PC
=min.
output open
CAS before RAS refresh cycling
t
RC
=min.
output open
RAS cycling CAS≤0.2V or CAS
before RAS refresh cycling
RAS≤0.2V or
≥V
CC
-0.2V
CAS≤0.2V or
≥V
CC
-0.2V
W≤0.2V or≥V
CC
-0.2V
OE≤0.2V or
≥V
CC
-0.2V
A
0
~A
8
≤
0.2V or
≥V
CC
-0.2V,
DQ=open
t
RC
=250µs, t
RAS
=t
RAS min
~1µs
RAS=CAS≤0.2V
output open
mA
I
CC3(AV)
M5M4V4265C-5,-5S
Average supply current
M5M4V4265C-6,-6S
from Vcc, RAS only
(Note 3,5)
M5M4V4265C-7,-7S
refresh mode
mA
I
CC4(AV)
I
CC6(AV)
Average supply current
from Vcc EDO mode
(Note 3,4,5)
Average supply current
from Vcc
CAS before RAS refresh
mode
(Note 3,5)
M5M4V4265C-5,-5S
M5M4V4265C-6,-6S
M5M4V4265C-7,-7S
M5M4V4265C-5,-5S
M5M4V4265C-6,-6S
M5M4V4265C-7,-7S
mA
mA
I
CC8(AV)
*
Average supply current
from V
CC
Extended-refresh mode
100
µA
(Note 6)
I
CC9(AV)
*
Average supply current from V
CC
Self-refresh mode
(Note 6)
100
µA
Note 2 : Current flowing into an IC is positive, out is negative.
3 : I
CC1(AV)
, I
CC3(AV)
, I
CC4(AV)
, and I
CC6 (AV)
are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
4 : I
CC1(AV)
and I
CC4(AV)
are dependent on output loading. Specified values are obtained with the output open.
5 : Column Address can be changed once or less while RAS=V
IL
and CAS=V
IH
.
3
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
CAPACITANCE
(Ta=0~70˚C, V
CC
=3.3±0.3V, V
SS
=0V, unless otherwise noted)
Symbol
C
I (A)
C
I (CLK)
C
I / O
Parameter
Input capacitance, address inputs
Input capacitance, clock inputs
Input/Output capacitance, data ports
Test conditions
V
I
=V
SS
f=1MHz
V
I
=25mVrms
Min
Limits
Typ
Max
5
7
7
Unit
pF
pF
pF
SWITCHING CHARACTERISTICS
(Ta=0~70˚C, V
CC
=3.3±0.3V, Vss=0V, unless otherwise noted, see notes 6,14,15)
Limits
Symbol
t
CAC
t
RAC
t
AA
t
CPA
t
OEA
t
OHC
t
OHR
t
CLZ
t
OEZ
t
WEZ
t
OFF
t
REZ
Parameter
Access time from CAS
Access time from RAS
Columu address access time
Access time from CAS precharge
Access time from OE
Output hold time from CAS
Output hold time from RAS
Output low impedance time from CAS low
Output disable time after OE high
Output disable time after WE high
Output disable time after CAS high
Output disable time after RAS high
(Note 7,8)
(Note 7,9)
(Note 7,10)
(Note 7,11)
(Note 7)
(Note 13)
(Note 13)
(Note 7)
(Note 12)
(Note 12)
(Note 12,13)
(Note 12,13)
M5M4V4265C-5,-5S
M5M4V4265C-6,-6S
M5M4V4265C-7,-7S
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min
Max
13
50
25
28
13
Min
Max
15
60
30
33
15
Min
Max
20
70
35
38
20
5
5
5
13
13
13
13
5
5
5
15
15
15
15
5
5
5
20
20
20
20
Note 6 : An initial pause of 500µs is required after power-up followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh
cycles).
Note the RAS may be cycled during the initial pause. And 8 initialization cycles are required after prolonged periods (greater than 8.2ms) of RAS
inactivity before proper device operation is achieved.
7 : Measured with a load circuit equivalent to 50pF, V
OH
(I
OH
=-2mA) and V
OL
(I
OL
=2mA). The reference levels for measuring of output signals are
2.0V(V
OH
) and 0.8V(V
OL
).
8 : Assumes that
t
RCD
≥t
RCD(max)
and
t
ASC
≥t
ASC(max)
and
t
CP
≥t
CP(max).
9 : Assumes that
t
RCD
≤t
RCD(max)
and
t
RAD
≤t
RAD(max)
. If
t
RCD
or
t
RAD
is greater than the maximum recommended value shown in this table,
t
RAC
will increase by amount that
t
RCD
exceeds the value shown.
10 : Assumes that
t
RAD
≥t
RAD(max)
and
t
ASC
≤t
ASC(max)
.
11 : Assumes that
t
CP
≤t
CP(max)
and
t
ASC
≥t
ASC(max)
.
12 :
t
OEZ (max)
,
t
WEZ(max)
,
t
OFF(max)
and
t
REZ(max)
defines the time at which the output achieves the high impedance state (I
OUT
≤
±5µA ) and is not
reference to V
OH(min)
or V
OL(max)
.
13 : Output is disabled after both RAS and CAS go to high.
4
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh and EDO Mode Cycles)
(Ta=0~70˚C, V
CC
=3.3±0.3V, V
SS
=0V, unless otherwise noted, see notes 14,15)
Limits
Symbol
t
REF
t
REF
t
RP
t
RCD
t
CRP
t
RPC
t
CPN
t
RAD
t
ASR
t
ASC
t
RAH
t
CAH
t
DZC
t
DZO
t
RDD
t
CDD
t
ODD
t
T
Parameter
M5M4V4265C-5,-5S
M5M4V4265C-6,-6S
M5M4V4265C-7,-7S
Unit
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min
Refresh cycle time
Refresh cycle time *
RAS high pulse width
Delay time, RAS low to CAS low
Delay time, CAS high to RAS low
Delay time, RAS high to CAS low
CAS high pulse width
Column address delay time from RAS low
Row address setup time before RAS low
Column address setup time before CAS low
Row address hold time after RAS low
Column address hold time after CAS low
Delay time, data to CAS low
Delay time, data to OE low
Delay time, RAS high to data
Delay time, CAS high to data
Delay time, OE high to data
Transition time
Note 14 : The timing requirements are assumed
t
T
=2ns.
Max
8.2
128
32
Min
Max
8.2
128
45
Min
Max
8.2
128
50
(Note 16)
(Note 17)
(Note 18)
(Note 19)
(Note 19)
(Note 20)
(Note 20)
(Note 20)
(Note 21)
30
18
5
0
8
13
0
0
8
8
0
0
13
13
13
1
25
10
50
40
20
5
0
10
15
0
0
10
10
0
0
15
15
15
1
30
13
50
50
20
5
0
10
15
0
0
10
10
0
0
20
20
20
1
35
13
50
Note
15 : V
IH(min)
and V
IL(max)
are reference levels for measuring timing of input signals.
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