MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Presettable 4-Bit Down Counters
The MC14522B BCD counter and the MC14526B binary counter are
constructed with MOS P–channel and N–channel enhancement mode
devices in a monolithic structure.
These devices are presettable, cascadable, synchronous down counters
with a decoded “0” state output for divide–by–N applications. In single stage
applications the “0” output is applied to the Preset Enable input. The
Cascade Feedback input allows cascade divide–by–N operation with no
additional gates required. The Inhibit input allows disabling of the pulse
counting function. Inhibit may also be used as a negative edge clock.
These complementary MOS counters can be used in frequency synthesiz-
ers, phase–locked loops, and other frequency division applications requiring
low power dissipation and/or high noise immunity.
•
Supply Voltage Range = 3.0 Vdc to 18 Vdc
•
Logic Edge–Clocked Design — Incremented on Positive Transition of
Clock or Negative Transition of Inhibit
•
Asynchronous Preset Enable
•
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS*
(Voltages Referenced to VSS)
Symbol
VDD
Parameter
DC Supply Voltage
Value
MC14522B
MC14526B
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Unit
V
V
– 0.5 to + 18.0
±
10
500
– 65 to + 150
260
Vin, Vout
Iin, Iout
PD
Tstg
TL
Input or Output Voltage (DC or Transient)
– 0.5 to VDD + 0.5
Input or Output Current (DC or Transient),
per Pin
Power Dissipation, per Package†
Storage Temperature
Lead Temperature (8–Second Soldering)
mA
mW
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
PIN ASSIGNMENT
Q3
P3
PE
INHIBIT
P0
CLOCK
Q0
VSS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
Q2
P2
CF
“0”
P1
RESET
Q1
_
C
_
C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/
_
C From 65
_
C To 125
_
C
Ceramic “L” Packages: – 12 mW/
_
C From 100
_
C To 125
_
C
FUNCTION TABLE
Inputs
Clock
X
X
X
X
L
H
H
Reset
H
H
H
L
L
L
L
L
L
L
Inhibit
X
X
X
X
H
L
L
Preset
Enable
L
H
X
H
L
L
L
L
L
L
Cascade
Feedback
L
L
H
X
X
X
L
L
L
L
Output
“0”
L
H
H
L
L
L
L
L
L
L
Resulting
Function
Asynchronous reset*
Asynchronous reset
Asynchronous reset
Asynchronous preset
Decrement inhibited
Decrement inhibited
No change** (inactive edge)
No change** (inactive edge)
Decrement**
Decrement**
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained
to the range VSS
(Vin or Vout)
VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
v
v
X = Don’t Care
NOTES:
* Output “0” is low when reset goes high only it PE and CF are low.
** Output “0” is high when reset is low, only if CF is high and count is 0000.
REV 3
1/94
©
MOTOROLA CMOS LOGIC DATA
Motorola, Inc. 1995
MC14522B MC14526B
1
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to VSS)
Characteristic
Symbol
VOL
VDD
Vdc
5.0
10
15
5.0
10
15
5.0
10
15
VIH
5.0
10
15
IOH
Source
5.0
5.0
10
15
IOL
5.0
10
15
15
—
5.0
10
15
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
0.64
1.6
4.2
—
—
—
—
—
—
—
—
—
—
—
—
±
0.1
—
5.0
10
20
– 2.4
– 0.51
– 1.3
– 3.4
0.51
1.3
3.4
—
—
—
—
—
– 4.2
– 0.88
– 2.25
– 8.8
0.88
2.25
8.8
±
0.00001
5.0
0.005
0.010
0.015
—
—
—
—
—
—
—
±
0.1
7.5
5.0
10
20
– 1.7
– 0.36
– 0.9
– 2.4
0.36
0.9
2.4
—
—
—
—
—
—
—
—
—
—
—
—
±
1.0
—
150
300
600
mAdc
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
mAdc
Min
—
—
—
– 55
_
C
25
_
C
125
_
C
Max
Min
—
—
—
Typ #
0
0
0
Max
Min
—
—
—
Max
Unit
Vdc
Output Voltage
Vin = VDD or 0
“0” Level
0.05
0.05
0.05
—
—
—
1.5
3.0
4.0
0.05
0.05
0.05
—
—
—
1.5
3.0
4.0
0.05
0.05
0.05
—
—
—
1.5
3.0
4.0
Vdc
“1” Level
Vin = 0 or VDD
Input Voltage
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Input Current
Input Capacitance
(Vin = 0)
Quiescent Current
(Per Package)
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
VIL
—
—
—
—
—
—
2.25
4.50
6.75
—
—
—
VOH
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Vdc
Sink
Iin
Cin
IDD
µAdc
pF
µAdc
IT
IT = (1.7
µA/kHz)
f + IDD
IT = (3.4
µA/kHz)
f + IDD
IT = (5.1
µA/kHz)
f + IDD
µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25
_
C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in
µA
(per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.
MC14522B MC14526B
2
MOTOROLA CMOS LOGIC DATA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS*
(CL = 50 pF, TA = 25
_
C)
Characteristic
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
Symbol
VDD
5.0
10
15
Min
—
—
—
Typ #
100
50
40
Max
200
100
80
Unit
ns
tTLH,
tTHL
(Figures 4, 5)
Propagation Delay Time (Inhibit Used as Negative
Edge Clock)
Clock or Inhibit to Q
tPLH, tPHL = (1.7 ns/pF) CL + 465 ns
tPLH, tPHL = (0.66 ns/pF) CL + 197 ns
tPLH, tPHL = (0.5 ns/pF) CL + 135 ns
Clock or Inhibit to “0”
tPLH, tPHL = (1.7 ns/pF) CL + 155 ns
tPLH, tPHL = (0.66 ns/pF) CL + 87 ns
tPLH, tPHL = (0.5 ns/pF) CL + 65 ns
Propagation Delay Time
Pn to Q
Propagation Delay Time
Reset to Q
Propagation Delay Time
Preset Enable to “0”
Clock or Inhibit Pulse Width
tPLH,
tPHL
(Figures 4, 7)
tPHL
(Figure 8)
tPHL,
tPLH
(Figures 4, 9)
tw
(Figures 5, 6)
Clock Pulse Frequency (with PE = low)
fmax
(Figures 4, 5, 6)
Clock or Inhibit Rise and Fall Time
tr,
tf
(Figures 5, 6)
tsu
(Figure 10)
Hold Time
Preset Enable to Pn
Preset Enable Pulse Width
th
(Figure 10)
tw
(Figure 10)
Reset Pulse Width
tw
(Figure 8)
Reset Removal Time
trem
(Figure 8)
tPLH,
tPHL
(Figures 4, 5, 6)
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
250
100
80
—
—
—
—
—
—
90
50
40
30
30
30
250
100
80
350
250
200
10
20
30
550
225
160
240
130
100
260
120
100
250
110
80
220
100
80
125
50
40
2.0
5.0
6.6
—
—
—
40
15
10
– 15
–5
0
125
50
40
175
125
100
– 110
– 30
– 20
1100
450
320
480
260
200
520
240
200
500
220
160
440
200
160
—
—
—
1.5
3.0
4.0
15
5
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
MHz
µs
Setup Time
Pn to Preset Enable
ns
ns
ns
ns
ns
* The formulas given are for the typical characteristics only at 25
_
C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
MOTOROLA CMOS LOGIC DATA
MC14522B MC14526B
3