SP6331, SP6333,
& SP6335
Quad
µPower
Supervisory Circuit
FEATURES
■
Low
operating voltage of 1.6V
■
Low operating current of 20µA typical
■
Monitors up to four supplies simultaneously
■
Adjustable inputs monitor down to 0.5V
■
Reset asserted down to 0.9V
■
2% accuracy over temperature range
■
Open Drain (OD) or CMOS Active Low
Reset (RSTB) output or CMOS RST output
■
4 Reset Timeout Periods:
50ms, 100ms, 200ms and 400 ms
■
6 Pin TSOT package
RSTB
GND
V4
6
5
4
SP6331
6 Pin TSOT
1
V1
2
V2
3
V3
Open Drain RESET
SEE PAGE 2 FOR OTHER
AVAILABLE PINOUTS
Available in Lead Free Packaging
DESCRIPTION
SP6331-SP6333-SP6335 Quad
µPower
Supervisory Circuits are a family of microprocessor
reset supervisory circuits with multiple reset voltages. The 3 device family provides low
voltage monitoring ability for up to four supplies with two precision factory-set thresholds and
two user defined custom thresholds. These circuits perform a single function: if any of the
input supply voltages drops below its associated threshold, reset outputs are asserted.
SP6331, SP6333 and SP6335 are packaged in a 6-pin TSOT package. All devices are fully
specified over -40
o
C to +85
o
C temperature range.
TYPICAL APPLICATION CIRCUIT
Date: 4/10/06 Rev H
SP6331-SP6333-SP6335 Quad
µPower
Supervisory Circuit
© Copyright 2006 Sipex Corporation
1
RSTB
GND
V4
RSTB
GND
V4
RSTB
GND
V4
6
5
4
6
5
4
6
5
4
SP6331
6 Pin TSOT
1
V1
SP6333
6 Pin TSOT
3
V3
SP6335
6 Pin TSOT
3
V3
2
V2
1
V1
2
V2
1
V1
2
V2
3
V3
OPEN DRAIN RESET
PART
NUMBER
SP6331
SP6333
SP6335
CMOS RESET
CMOS RESET
V1
√
√
√
V2
√
√
√
V3
√
√
√
V4
√
√
√
Reset
OD Active Low
CMOS Active Low
CMOS Active High
Feature and Pinout Diagram
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation
of the device at these ratings or any other above those
indicated in the operation sections of the specifica-
tions below is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods of time
may affect reliability and cause permanent damage to
the device.
Terminal Voltage (with respect to GND)
V1, V2.................................................. -0.3 to +6V
V3, V4............................................-0.3 to (V1+0.3V)
Open-Drain RSTB, .............................-0.3 to +6V
CMOS RST, RSTB....................... -0.3 to (V1+0.3V)
Input Current/Output
Current.................................,,........................20mA
Operating Temperature
Range...............................................-40°C to +85°C
Storage Temperature
Range...............................................-65°C to 150°C
Thermal Resistance
Θ
JA
..............................134°C/W
Date: 4/10/06 Rev H
SP6331-SP6333-SP6335 Quad
µPower
Supervisory Circuit
© Copyright 2006 Sipex Corporation
2
ELECTRICAL CHARACTERISTICS
PARAMETER
Operating
Range
Voltage
MIN
0.9
TYP
MAX
5.5
UNITS
CONDITIONS
T
A
= -40ºC to +85ºC
V1 < 5.5V, V2 < 3.60V, all I/O
pins open
V1 < 3.6V, V2 < 2.75V, all I/O
pins open
Z (valid for V1 falling)
Y (valid for V1 falling)
X (valid for V1 falling)
W (valid for V1 falling)
V (valid for V1 falling)
U (valid for V1 falling)
T (valid for V1 falling)
S (valid for V1 falling)
R (valid for V1 falling)
J (valid for V2 falling)
I (valid for V2 falling)
H (valid for V2 falling)
G (valid for V2 falling)
F (valid for V2 falling)
E (valid for V2 falling)
D (valid for V2 falling)
C (valid for V2 falling)
B (valid for V2 falling)
A (valid for V2 falling)
V1 =1.6V to 5.5V; TA = -40ºC to +85ºC; unless otherwise noted. Typical values are at TA =+25ºC
V
uA
20
Supply Current
15
4.532
4.287
3.013
2.866
2.572
2.273
2.146
1.636
1.548
2.266
2.144
1.631
1.543
1.360
1.286
1.087
1.029
0.816
0.772
4.625
4.375
3.075
2.925
2.625
2.320
2.190
1.670
1.580
2.313
2.188
1.665
1.575
1.388
1.313
1.110
1.050
0.833
0.788
0.06
0.04
0.64
0.5
50
50
37
74
148
296
50
100
200
400
30
25
4.718
4.463
3.137
2.984
2.678
2.367
2.234
1.704
1.612
2.360
2.232
1.698
1.607
1.416
1.340
1.133
1.071
0.850
0.804
V1 Reset Threshold
V
V2 Reset Threshold
V
Threshold 1
Tempco
Threshold 2
Tempco
Threshold 1
Hysteresis
Threshold 2
Hysteresis
V1 to RST/RSTB
Delay
V2 to RST/RSTB
Delay
Reset Timeout
Period (T1)
Reset Timeout
Period (T2)
Reset Timeout
Period (T3)
Reset Timeout
Period (T4)
Date: 4/10/06 Rev H
mV/ºC
mV/ºC
%
%
us
us
63
126
252
504
ms
ms
ms
ms
reference to Vth1 typical
reference to Vth2 typical
V1 = Vth1 to (Vth1-0.1V), Vth1
= 3.075
V2 = Vth2 to (Vth2-0.1V), Vth2
= 1.575
TOPT-1
TOPT-2
TOPT-3
TOPT-4
© Copyright 2006 Sipex Corporation
SP6331-SP6333-SP6335 Quad
µPower
Supervisory Circuit
3
ELECTRICAL CHARACTERISTICS (CONT'D)
PARAMETER
MIN
TYP
MAX
UNITS
CONDITIONS
V1 =1.6V to 5.5V; TA = -40ºC to +85ºC; unless otherwise noted. Typical values are at TA =+25ºC
V3 RESET COMPARATOR INPUT
V3 Input Threshold
490
500
V3 Input Current
-50
V3 Threshold
1.5
Hysteresis
V4 RESET COMPARATOR INPUT
V4 Input Threshold
490
500
V4 Input Current
-50
V4 Threshold
Hysteresis
RESET OUTPUTS RST / RSTB
RSTB
(CMOS or OD)
RSTB (CMOS)
RST (CMOS)
RST (CMOS)
RSTB Output OD
Leakage Current
2
0.8*V1
0.8*V1
510
50
mV
nA
mV
T
A
= +25ºC
510
50
mV
nA
mV
T
A
= +25ºC
1.5
0.4
V
V
V
0.4
V
nA
V1 = Vth1 - 0.1V, Isink = 1mA,
output asserted
V1 = Vth1 + 0.1V, Isource =
1mA, output not asserted
V1 = Vth1 - 0.1V, Isource =
1mA, output asserted
V1 = Vth1 + 0.1V, V2 > Vth2,
V3 > 0.5, V4 > 0.5, Isource =
1mA, output not asserted
T
A
= +25ºC
PIN DESCRIPTION
Pin #
1
2
3
4
5
Name
V1
V2
V3
V4
GND
Description
First supply voltage input. Also powers internal circuitry. Trip
threshold voltage internally set.
Second supply voltage input. Trip threshold voltage internally set.
Input for the third supply voltage. Trip threshold is 0.5V.
Input for the fourth supply voltage. Trip threshold is 0.5V.
Common ground reference pin.
Reset output. Open-Drain or CMOS, active high or low. Reset is
asserted when any of the four supply inputs is below its trip
threshold. It stays asserted for 200 ms (typical / default) after the last
supply input traverses its trip threshold. Reset is guaranteed to be in
the correct state for V1>0.9V. RST/RSTB asserts when V1 or V2 or
V3 or V4 drop below their corresponding reset thresholds.
RST/RSTB remains asserted for the reset timeout period after V1
and V2 and V3 and V4 exceed their corresponding reset thresholds.
Open-drain outputs require an external pull-up resistor. CMOS
outputs are referenced to V1.
© Copyright 2006 Sipex Corporation
6
RST/RSTB
Date: 4/10/06 Rev H
SP6331-SP6333-SP6335 Quad
µPower
Supervisory Circuit
4
THEORY OF OPERATION
V1
V2
V3
V4
OSC
Band
Gap
Ref
1.25V
CONTROL
LOGIC
0.5V
RSTB (RST)
Block Diagram
GND
The SP6331, SP6333, and SP6335 include
a low-voltage precision bandgap reference,
four precision comparators, an oscillator, a
digital counter chain, a logic control block,
trimmed resistor divider chains and
additional supporting circuitry. The family is
designed to supervise up to 4 independent
supply voltages. V1 and V2 supply inputs
have their resistor dividers on the chip.
Their trip thresholds are factory trimmed.
V3 and V4 inputs allow user to customize
two additional supply thresholds to be
monitored by means of external resistor
dividers.
Date: 4/10/06 Rev H
SP6331-SP6333-SP6335 Quad
µPower
Supervisory Circuit
© Copyright 2006 Sipex Corporation
5
Wireless Connectivity
京公网安备 11010802033920号
EEWORLD
